410f4c60ad
o Separate TX/RX buffer DMA tag from TX/RX descriptor ring DMA tag. o Separate RX buffer DMA tag from common buffer DMA tag. RX DMA tag has different restriction compared to TX DMA tag. o Add 40bit DMA address support. o Adjust TX/RX descriptor ring alignment to 64 bytes from 256 bytes as documented in datasheet. o Added check to ensure TX/RX ring reside within a 4GB boundary. Since TX/RX ring shares the same high address register they should have the same high address. o TX/RX side bus_dmamap_load_mbuf_sg(9) support. o Add lock assertion to vge_setmulti(). o Add RX spare DMA map to recover from DMA map load failure. o Add optimized RX buffer handler, vge_discard_rxbuf which is activated when vge(4) sees bad frames. o Don't blindly update VGE_RXDESC_RESIDUECNT register. Datasheet says the register should be updated only when number of available RX descriptors are multiple of 4. o Use __NO_STRICT_ALIGNMENT instead of defining VGE_FIXUP_RX which is only set for i386 architecture. Previously vge(4) also performed expensive copy operation to align IP header on amd64. This change should give RX performance boost on amd64 architecture. o Don't reinitialize controller if driver is already running. This should reduce number of link state flipping. o Since vge(4) drops a driver lock before passing received frame to upper layer, make sure vge(4) is still running after re-acquiring driver lock. o Add second argument count to vge_rxeof(). The argument will limit number of packets could be processed in RX handler. o Rearrange vge_rxeof() not to allocate RX buffer if received frame was bad packet. o Removed if_printf that prints DMA map failure. This type of message shouldn't be used in fast path of driver. o Reduce number of allowed TX buffer fragments to 6 from 7. A TX descriptor allows 7 fragments of a frame. However the CMZ field of descriptor has just 3bits and the controller wants to see fragment + 1 in the field. So if we have 7 fragments the field value would be 0 which seems to cause unexpected results under certain conditions. This change should fix occasional TX hang observed on vge(4). o Simplify vge_stat_locked() and add number of available TX descriptor check. o vge(4) controllers lack padding short frames. Make sure to fill zero for the padded bytes. This closes unintended information disclosure. o Don't set VGE_TDCTL_JUMBO flag. Datasheet is not clear whether this bit should be set by driver or write-back status bit after transmission. At least vendor's driver does not set this bit so remove it. Without this bit vge(4) still can send jumbo frames. o Don't start driver when vge(4) know there are not enough RX buffers. o Remove volatile keyword in RX descriptor structure. This should be handled by bus_dma(9). o Collapse two 16bits member of TX/RX descriptor into single 32bits member. o Reduce number of RX descriptors to 252 from 256. The VGE_RXDESCNUM is 16bits register but only lower 8bits are valid. So the maximum number of RX descriptors would be 255. However the number of should be multiple of 4 as controller wants to update 4 RX descriptors at a time. This limits the maximum number of RX descriptor to be 252. Tested by: Dewayne Geraghty (dewayne.geraghty <> heuristicsystems dot com dot au) Carey Jones (m.carey.jones <> gmail dot com) Yoshiaki Kasahara (kasahara <> nc dor kyushu-u dot ac dotjp)
196 lines
6.0 KiB
C
196 lines
6.0 KiB
C
/*-
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* Copyright (c) 2004
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* Bill Paul <wpaul@windriver.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define VGE_JUMBO_MTU 9000
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#define VGE_IFQ_MAXLEN 64
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#define VGE_TX_DESC_CNT 256
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#define VGE_RX_DESC_CNT 252 /* Must be a multiple of 4!! */
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#define VGE_TX_RING_ALIGN 64
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#define VGE_RX_RING_ALIGN 64
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#define VGE_MAXTXSEGS 6
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#define VGE_RX_BUF_ALIGN sizeof(uint32_t)
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/*
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* VIA Velocity allows 64bit DMA addressing but high 16bits
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* of the DMA address should be the same for Tx/Rx buffers.
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* Because this condition can't be guaranteed vge(4) limit
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* DMA address space to 48bits.
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*/
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#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
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#define VGE_BUF_DMA_MAXADDR BUS_SPACE_MAXADDR
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#else
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#define VGE_BUF_DMA_MAXADDR 0xFFFFFFFFFFFF
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#endif
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#define VGE_RX_LIST_SZ (VGE_RX_DESC_CNT * sizeof(struct vge_rx_desc))
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#define VGE_TX_LIST_SZ (VGE_TX_DESC_CNT * sizeof(struct vge_tx_desc))
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#define VGE_TX_DESC_INC(x) ((x) = ((x) + 1) % VGE_TX_DESC_CNT)
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#define VGE_TX_DESC_DEC(x) \
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((x) = (((x) + VGE_TX_DESC_CNT - 1) % VGE_TX_DESC_CNT))
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#define VGE_RX_DESC_INC(x) ((x) = ((x) + 1) % VGE_RX_DESC_CNT)
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#define VGE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
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#define VGE_ADDR_HI(y) ((uint64_t) (y) >> 32)
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#define VGE_BUFLEN(y) ((y) & 0x3FFF)
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#define VGE_RXBYTES(x) (((x) & VGE_RDSTS_BUFSIZ) >> 16)
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#define VGE_MIN_FRAMELEN 60
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#ifdef VGE_FIXUP_RX
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#define VGE_ETHER_ALIGN sizeof(uint32_t)
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#else
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#define VGE_ETHER_ALIGN 0
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#endif
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struct vge_type {
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uint16_t vge_vid;
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uint16_t vge_did;
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char *vge_name;
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};
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struct vge_txdesc {
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struct mbuf *tx_m;
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bus_dmamap_t tx_dmamap;
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struct vge_tx_desc *tx_desc;
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struct vge_txdesc *txd_prev;
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};
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struct vge_rxdesc {
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struct mbuf *rx_m;
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bus_dmamap_t rx_dmamap;
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struct vge_rx_desc *rx_desc;
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struct vge_rxdesc *rxd_prev;
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};
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struct vge_chain_data{
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bus_dma_tag_t vge_ring_tag;
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bus_dma_tag_t vge_buffer_tag;
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bus_dma_tag_t vge_tx_tag;
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struct vge_txdesc vge_txdesc[VGE_TX_DESC_CNT];
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bus_dma_tag_t vge_rx_tag;
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struct vge_rxdesc vge_rxdesc[VGE_RX_DESC_CNT];
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bus_dma_tag_t vge_tx_ring_tag;
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bus_dmamap_t vge_tx_ring_map;
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bus_dma_tag_t vge_rx_ring_tag;
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bus_dmamap_t vge_rx_ring_map;
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bus_dmamap_t vge_rx_sparemap;
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int vge_tx_prodidx;
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int vge_tx_considx;
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int vge_tx_cnt;
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int vge_rx_prodidx;
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int vge_rx_commit;
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struct mbuf *vge_head;
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struct mbuf *vge_tail;
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};
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#define VGE_CHAIN_RESET(_sc) \
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do { \
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if ((_sc)->vge_cdata.vge_head != NULL) { \
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m_freem((_sc)->vge_cdata.vge_head); \
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(_sc)->vge_cdata.vge_head = NULL; \
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(_sc)->vge_cdata.vge_tail = NULL; \
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} \
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} while (0);
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struct vge_ring_data {
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struct vge_tx_desc *vge_tx_ring;
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bus_addr_t vge_tx_ring_paddr;
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struct vge_rx_desc *vge_rx_ring;
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bus_addr_t vge_rx_ring_paddr;
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};
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struct vge_softc {
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struct ifnet *vge_ifp; /* interface info */
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device_t vge_dev;
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struct resource *vge_res;
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struct resource *vge_irq;
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void *vge_intrhand;
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device_t vge_miibus;
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u_int8_t vge_type;
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int vge_if_flags;
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int vge_link;
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int vge_camidx;
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struct mtx vge_mtx;
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struct callout vge_watchdog;
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int vge_timer;
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struct vge_chain_data vge_cdata;
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struct vge_ring_data vge_rdata;
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int suspended; /* 0 = normal 1 = suspended */
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};
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#define VGE_LOCK(_sc) mtx_lock(&(_sc)->vge_mtx)
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#define VGE_UNLOCK(_sc) mtx_unlock(&(_sc)->vge_mtx)
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#define VGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vge_mtx, MA_OWNED)
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/*
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* register space access macros
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*/
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#define CSR_WRITE_STREAM_4(sc, reg, val) \
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bus_write_stream_4(sc->vge_res, reg, val)
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#define CSR_WRITE_4(sc, reg, val) \
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bus_write_4(sc->vge_res, reg, val)
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#define CSR_WRITE_2(sc, reg, val) \
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bus_write_2(sc->vge_res, reg, val)
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#define CSR_WRITE_1(sc, reg, val) \
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bus_write_1(sc->vge_res, reg, val)
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#define CSR_READ_4(sc, reg) \
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bus_read_4(sc->vge_res, reg)
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#define CSR_READ_2(sc, reg) \
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bus_read_2(sc->vge_res, reg)
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#define CSR_READ_1(sc, reg) \
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bus_read_1(sc->vge_res, reg)
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#define CSR_SETBIT_1(sc, reg, x) \
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CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
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#define CSR_SETBIT_2(sc, reg, x) \
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CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
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#define CSR_SETBIT_4(sc, reg, x) \
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CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
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#define CSR_CLRBIT_1(sc, reg, x) \
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CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
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#define CSR_CLRBIT_2(sc, reg, x) \
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CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
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#define CSR_CLRBIT_4(sc, reg, x) \
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CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
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#define VGE_RXCHUNK 4
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#define VGE_TIMEOUT 10000
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