4aaefb9559
EFSYS_MEM_SIZE() reports the DMA mapped size of an efsys_mem_t allocated region (the allocation size may be different due to memory allocator and DMA alignment restrictions). This ensures that common code internals have explicit knowledge of the usable size of DMA mapped memory regions. Submitted by: Andy Moreton <amoreton at solarflare.com> Sponsored by: Solarflare Communications, Inc. Differential Revision: https://reviews.freebsd.org/D18170
595 lines
15 KiB
C
595 lines
15 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2007-2016 Solarflare Communications Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation are
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* those of the authors and should not be interpreted as representing official
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* policies, either expressed or implied, of the FreeBSD Project.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "efx.h"
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#include "efx_impl.h"
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#if EFSYS_OPT_SIENA
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static __checkReturn efx_rc_t
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siena_intr_init(
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__in efx_nic_t *enp,
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__in efx_intr_type_t type,
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__in efsys_mem_t *esmp);
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static void
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siena_intr_enable(
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__in efx_nic_t *enp);
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static void
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siena_intr_disable(
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__in efx_nic_t *enp);
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static void
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siena_intr_disable_unlocked(
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__in efx_nic_t *enp);
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static __checkReturn efx_rc_t
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siena_intr_trigger(
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__in efx_nic_t *enp,
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__in unsigned int level);
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static void
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siena_intr_fini(
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__in efx_nic_t *enp);
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static void
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siena_intr_status_line(
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__in efx_nic_t *enp,
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__out boolean_t *fatalp,
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__out uint32_t *qmaskp);
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static void
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siena_intr_status_message(
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__in efx_nic_t *enp,
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__in unsigned int message,
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__out boolean_t *fatalp);
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static void
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siena_intr_fatal(
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__in efx_nic_t *enp);
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static __checkReturn boolean_t
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siena_intr_check_fatal(
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__in efx_nic_t *enp);
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#endif /* EFSYS_OPT_SIENA */
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#if EFSYS_OPT_SIENA
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static const efx_intr_ops_t __efx_intr_siena_ops = {
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siena_intr_init, /* eio_init */
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siena_intr_enable, /* eio_enable */
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siena_intr_disable, /* eio_disable */
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siena_intr_disable_unlocked, /* eio_disable_unlocked */
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siena_intr_trigger, /* eio_trigger */
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siena_intr_status_line, /* eio_status_line */
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siena_intr_status_message, /* eio_status_message */
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siena_intr_fatal, /* eio_fatal */
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siena_intr_fini, /* eio_fini */
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};
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#endif /* EFSYS_OPT_SIENA */
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#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
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static const efx_intr_ops_t __efx_intr_ef10_ops = {
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ef10_intr_init, /* eio_init */
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ef10_intr_enable, /* eio_enable */
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ef10_intr_disable, /* eio_disable */
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ef10_intr_disable_unlocked, /* eio_disable_unlocked */
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ef10_intr_trigger, /* eio_trigger */
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ef10_intr_status_line, /* eio_status_line */
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ef10_intr_status_message, /* eio_status_message */
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ef10_intr_fatal, /* eio_fatal */
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ef10_intr_fini, /* eio_fini */
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};
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#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
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__checkReturn efx_rc_t
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efx_intr_init(
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__in efx_nic_t *enp,
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__in efx_intr_type_t type,
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__in efsys_mem_t *esmp)
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{
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efx_intr_t *eip = &(enp->en_intr);
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const efx_intr_ops_t *eiop;
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efx_rc_t rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
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if (enp->en_mod_flags & EFX_MOD_INTR) {
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rc = EINVAL;
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goto fail1;
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}
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eip->ei_esmp = esmp;
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eip->ei_type = type;
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eip->ei_level = 0;
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enp->en_mod_flags |= EFX_MOD_INTR;
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switch (enp->en_family) {
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#if EFSYS_OPT_SIENA
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case EFX_FAMILY_SIENA:
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eiop = &__efx_intr_siena_ops;
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break;
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#endif /* EFSYS_OPT_SIENA */
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#if EFSYS_OPT_HUNTINGTON
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case EFX_FAMILY_HUNTINGTON:
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eiop = &__efx_intr_ef10_ops;
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break;
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#endif /* EFSYS_OPT_HUNTINGTON */
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#if EFSYS_OPT_MEDFORD
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case EFX_FAMILY_MEDFORD:
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eiop = &__efx_intr_ef10_ops;
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break;
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#endif /* EFSYS_OPT_MEDFORD */
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#if EFSYS_OPT_MEDFORD2
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case EFX_FAMILY_MEDFORD2:
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eiop = &__efx_intr_ef10_ops;
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break;
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#endif /* EFSYS_OPT_MEDFORD2 */
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default:
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EFSYS_ASSERT(B_FALSE);
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rc = ENOTSUP;
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goto fail2;
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}
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if ((rc = eiop->eio_init(enp, type, esmp)) != 0)
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goto fail3;
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eip->ei_eiop = eiop;
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return (0);
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fail3:
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EFSYS_PROBE(fail3);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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void
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efx_intr_fini(
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__in efx_nic_t *enp)
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{
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efx_intr_t *eip = &(enp->en_intr);
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const efx_intr_ops_t *eiop = eip->ei_eiop;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
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eiop->eio_fini(enp);
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enp->en_mod_flags &= ~EFX_MOD_INTR;
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}
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void
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efx_intr_enable(
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__in efx_nic_t *enp)
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{
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efx_intr_t *eip = &(enp->en_intr);
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const efx_intr_ops_t *eiop = eip->ei_eiop;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
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eiop->eio_enable(enp);
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}
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void
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efx_intr_disable(
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__in efx_nic_t *enp)
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{
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efx_intr_t *eip = &(enp->en_intr);
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const efx_intr_ops_t *eiop = eip->ei_eiop;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
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eiop->eio_disable(enp);
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}
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void
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efx_intr_disable_unlocked(
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__in efx_nic_t *enp)
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{
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efx_intr_t *eip = &(enp->en_intr);
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const efx_intr_ops_t *eiop = eip->ei_eiop;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
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eiop->eio_disable_unlocked(enp);
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}
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__checkReturn efx_rc_t
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efx_intr_trigger(
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__in efx_nic_t *enp,
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__in unsigned int level)
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{
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efx_intr_t *eip = &(enp->en_intr);
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const efx_intr_ops_t *eiop = eip->ei_eiop;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
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return (eiop->eio_trigger(enp, level));
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}
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void
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efx_intr_status_line(
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__in efx_nic_t *enp,
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__out boolean_t *fatalp,
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__out uint32_t *qmaskp)
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{
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efx_intr_t *eip = &(enp->en_intr);
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const efx_intr_ops_t *eiop = eip->ei_eiop;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
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eiop->eio_status_line(enp, fatalp, qmaskp);
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}
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void
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efx_intr_status_message(
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__in efx_nic_t *enp,
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__in unsigned int message,
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__out boolean_t *fatalp)
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{
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efx_intr_t *eip = &(enp->en_intr);
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const efx_intr_ops_t *eiop = eip->ei_eiop;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
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eiop->eio_status_message(enp, message, fatalp);
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}
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void
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efx_intr_fatal(
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__in efx_nic_t *enp)
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{
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efx_intr_t *eip = &(enp->en_intr);
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const efx_intr_ops_t *eiop = eip->ei_eiop;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
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eiop->eio_fatal(enp);
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}
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/* ************************************************************************* */
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/* ************************************************************************* */
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/* ************************************************************************* */
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#if EFSYS_OPT_SIENA
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static __checkReturn efx_rc_t
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siena_intr_init(
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__in efx_nic_t *enp,
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__in efx_intr_type_t type,
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__in efsys_mem_t *esmp)
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{
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efx_intr_t *eip = &(enp->en_intr);
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efx_oword_t oword;
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efx_rc_t rc;
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if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_INTR_SIZE)) {
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rc = EINVAL;
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goto fail1;
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}
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/*
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* bug17213 workaround.
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*
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* Under legacy interrupts, don't share a level between fatal
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* interrupts and event queue interrupts. Under MSI-X, they
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* must share, or we won't get an interrupt.
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*/
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if (enp->en_family == EFX_FAMILY_SIENA &&
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eip->ei_type == EFX_INTR_LINE)
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eip->ei_level = 0x1f;
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else
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eip->ei_level = 0;
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/* Enable all the genuinely fatal interrupts */
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EFX_SET_OWORD(oword);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_ILL_ADR_INT_KER_EN, 0);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_RBUF_OWN_INT_KER_EN, 0);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_TBUF_OWN_INT_KER_EN, 0);
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if (enp->en_family >= EFX_FAMILY_SIENA)
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EFX_SET_OWORD_FIELD(oword, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 0);
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EFX_BAR_WRITEO(enp, FR_AZ_FATAL_INTR_REG_KER, &oword);
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/* Set up the interrupt address register */
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EFX_POPULATE_OWORD_3(oword,
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FRF_AZ_NORM_INT_VEC_DIS_KER, (type == EFX_INTR_MESSAGE) ? 1 : 0,
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FRF_AZ_INT_ADR_KER_DW0, EFSYS_MEM_ADDR(esmp) & 0xffffffff,
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FRF_AZ_INT_ADR_KER_DW1, EFSYS_MEM_ADDR(esmp) >> 32);
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EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);
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return (0);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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static void
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siena_intr_enable(
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__in efx_nic_t *enp)
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{
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efx_intr_t *eip = &(enp->en_intr);
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efx_oword_t oword;
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EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 1);
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EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
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}
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static void
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siena_intr_disable(
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__in efx_nic_t *enp)
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{
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efx_oword_t oword;
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EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);
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EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
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EFSYS_SPIN(10);
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}
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static void
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siena_intr_disable_unlocked(
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__in efx_nic_t *enp)
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{
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efx_oword_t oword;
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EFSYS_BAR_READO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,
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&oword, B_FALSE);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);
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EFSYS_BAR_WRITEO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,
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&oword, B_FALSE);
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}
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static __checkReturn efx_rc_t
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siena_intr_trigger(
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__in efx_nic_t *enp,
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__in unsigned int level)
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{
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efx_intr_t *eip = &(enp->en_intr);
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efx_oword_t oword;
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unsigned int count;
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uint32_t sel;
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efx_rc_t rc;
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/* bug16757: No event queues can be initialized */
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EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
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if (level >= EFX_NINTR_SIENA) {
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rc = EINVAL;
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goto fail1;
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}
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if (level > EFX_MASK32(FRF_AZ_KER_INT_LEVE_SEL))
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return (ENOTSUP); /* avoid EFSYS_PROBE() */
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sel = level;
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/* Trigger a test interrupt */
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EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, sel);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER, 1);
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EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
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/*
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* Wait up to 100ms for the interrupt to be raised before restoring
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* KER_INT_LEVE_SEL. Ignore a failure to raise (the caller will
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* observe this soon enough anyway), but always reset KER_INT_LEVE_SEL
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*/
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count = 0;
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do {
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EFSYS_SPIN(100); /* 100us */
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EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
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} while (EFX_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER) && ++count < 1000);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);
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EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
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return (0);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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static __checkReturn boolean_t
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siena_intr_check_fatal(
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__in efx_nic_t *enp)
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{
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efx_intr_t *eip = &(enp->en_intr);
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efsys_mem_t *esmp = eip->ei_esmp;
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efx_oword_t oword;
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|
|
|
/* Read the syndrome */
|
|
EFSYS_MEM_READO(esmp, 0, &oword);
|
|
|
|
if (EFX_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT) != 0) {
|
|
EFSYS_PROBE(fatal);
|
|
|
|
/* Clear the fatal interrupt condition */
|
|
EFX_SET_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT, 0);
|
|
EFSYS_MEM_WRITEO(esmp, 0, &oword);
|
|
|
|
return (B_TRUE);
|
|
}
|
|
|
|
return (B_FALSE);
|
|
}
|
|
|
|
static void
|
|
siena_intr_status_line(
|
|
__in efx_nic_t *enp,
|
|
__out boolean_t *fatalp,
|
|
__out uint32_t *qmaskp)
|
|
{
|
|
efx_intr_t *eip = &(enp->en_intr);
|
|
efx_dword_t dword;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
|
|
|
|
/*
|
|
* Read the queue mask and implicitly acknowledge the
|
|
* interrupt.
|
|
*/
|
|
EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE);
|
|
*qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
|
|
|
|
EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
|
|
|
|
if (*qmaskp & (1U << eip->ei_level))
|
|
*fatalp = siena_intr_check_fatal(enp);
|
|
else
|
|
*fatalp = B_FALSE;
|
|
}
|
|
|
|
static void
|
|
siena_intr_status_message(
|
|
__in efx_nic_t *enp,
|
|
__in unsigned int message,
|
|
__out boolean_t *fatalp)
|
|
{
|
|
efx_intr_t *eip = &(enp->en_intr);
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
|
|
|
|
if (message == eip->ei_level)
|
|
*fatalp = siena_intr_check_fatal(enp);
|
|
else
|
|
*fatalp = B_FALSE;
|
|
}
|
|
|
|
|
|
static void
|
|
siena_intr_fatal(
|
|
__in efx_nic_t *enp)
|
|
{
|
|
#if EFSYS_OPT_DECODE_INTR_FATAL
|
|
efx_oword_t fatal;
|
|
efx_oword_t mem_per;
|
|
|
|
EFX_BAR_READO(enp, FR_AZ_FATAL_INTR_REG_KER, &fatal);
|
|
EFX_ZERO_OWORD(mem_per);
|
|
|
|
if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0 ||
|
|
EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0)
|
|
EFX_BAR_READO(enp, FR_AZ_MEM_STAT_REG, &mem_per);
|
|
|
|
if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRAM_OOB_INT_KER) != 0)
|
|
EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_OOB, 0, 0);
|
|
|
|
if (EFX_OWORD_FIELD(fatal, FRF_AZ_BUFID_DC_OOB_INT_KER) != 0)
|
|
EFSYS_ERR(enp->en_esip, EFX_ERR_BUFID_DC_OOB, 0, 0);
|
|
|
|
if (EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0)
|
|
EFSYS_ERR(enp->en_esip, EFX_ERR_MEM_PERR,
|
|
EFX_OWORD_FIELD(mem_per, EFX_DWORD_0),
|
|
EFX_OWORD_FIELD(mem_per, EFX_DWORD_1));
|
|
|
|
if (EFX_OWORD_FIELD(fatal, FRF_AZ_RBUF_OWN_INT_KER) != 0)
|
|
EFSYS_ERR(enp->en_esip, EFX_ERR_RBUF_OWN, 0, 0);
|
|
|
|
if (EFX_OWORD_FIELD(fatal, FRF_AZ_TBUF_OWN_INT_KER) != 0)
|
|
EFSYS_ERR(enp->en_esip, EFX_ERR_TBUF_OWN, 0, 0);
|
|
|
|
if (EFX_OWORD_FIELD(fatal, FRF_AZ_RDESCQ_OWN_INT_KER) != 0)
|
|
EFSYS_ERR(enp->en_esip, EFX_ERR_RDESQ_OWN, 0, 0);
|
|
|
|
if (EFX_OWORD_FIELD(fatal, FRF_AZ_TDESCQ_OWN_INT_KER) != 0)
|
|
EFSYS_ERR(enp->en_esip, EFX_ERR_TDESQ_OWN, 0, 0);
|
|
|
|
if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVQ_OWN_INT_KER) != 0)
|
|
EFSYS_ERR(enp->en_esip, EFX_ERR_EVQ_OWN, 0, 0);
|
|
|
|
if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVF_OFLO_INT_KER) != 0)
|
|
EFSYS_ERR(enp->en_esip, EFX_ERR_EVFF_OFLO, 0, 0);
|
|
|
|
if (EFX_OWORD_FIELD(fatal, FRF_AZ_ILL_ADR_INT_KER) != 0)
|
|
EFSYS_ERR(enp->en_esip, EFX_ERR_ILL_ADDR, 0, 0);
|
|
|
|
if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0)
|
|
EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_PERR,
|
|
EFX_OWORD_FIELD(mem_per, EFX_DWORD_0),
|
|
EFX_OWORD_FIELD(mem_per, EFX_DWORD_1));
|
|
#else
|
|
EFSYS_ASSERT(0);
|
|
#endif
|
|
}
|
|
|
|
static void
|
|
siena_intr_fini(
|
|
__in efx_nic_t *enp)
|
|
{
|
|
efx_oword_t oword;
|
|
|
|
/* Clear the interrupt address register */
|
|
EFX_ZERO_OWORD(oword);
|
|
EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);
|
|
}
|
|
|
|
#endif /* EFSYS_OPT_SIENA */
|