532 lines
14 KiB
C
532 lines
14 KiB
C
/*-
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _SCIC_SDS_PHY_H_
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#define _SCIC_SDS_PHY_H_
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/**
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* @file
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*
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* @brief This file contains the structures, constants and prototypes for the
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* SCIC_SDS_PHY object.
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif // __cplusplus
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#include <dev/isci/scil/intel_sata.h>
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#include <dev/isci/scil/intel_sas.h>
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#include <dev/isci/scil/sci_base_phy.h>
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#include <dev/isci/scil/scu_registers.h>
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#include <dev/isci/scil/scu_event_codes.h>
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/**
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* This is the timeout value for the SATA phy to wait for a SIGNATURE FIS
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* before restarting the starting state machine. Technically, the old
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* parallel ATA specification required up to 30 seconds for a device to
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* issue its signature FIS as a result of a soft reset. Now we see that
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* devices respond generally within 15 seconds, but we'll use 25 for now.
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*/
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#define SCIC_SDS_SIGNATURE_FIS_TIMEOUT 25000
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/**
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* This is the timeout for the SATA OOB/SN because the hardware does not
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* recognize a hot plug after OOB signal but before the SN signals. We
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* need to make sure after a hotplug timeout if we have not received the
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* speed event notification from the hardware that we restart the hardware
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* OOB state machine.
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*/
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#define SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT 250
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/**
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* @enum SCIC_SDS_PHY_STARTING_SUBSTATES
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*/
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enum SCIC_SDS_PHY_STARTING_SUBSTATES
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{
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/**
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* Initial state
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*/
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SCIC_SDS_PHY_STARTING_SUBSTATE_INITIAL,
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/**
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* Wait state for the hardware OSSP event type notification
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*/
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SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_OSSP_EN,
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/**
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* Wait state for the PHY speed notification
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*/
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SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_SPEED_EN,
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/**
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* Wait state for the IAF Unsolicited frame notification
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*/
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SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF,
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/**
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* Wait state for the request to consume power
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*/
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SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_POWER,
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/**
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* Wait state for request to consume power
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*/
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SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_POWER,
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/**
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* Wait state for the SATA PHY notification
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*/
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SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_PHY_EN,
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/**
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* Wait for the SATA PHY speed notification
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*/
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SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN,
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/**
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* Wait state for the SIGNATURE FIS unsolicited frame notification
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*/
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SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF,
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/**
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* Exit state for this state machine
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*/
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SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL,
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/**
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* Maximum number of substates for the STARTING state machine
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*/
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SCIC_SDS_PHY_STARTING_MAX_SUBSTATES
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};
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struct SCIC_SDS_PORT;
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struct SCIC_SDS_CONTROLLER;
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#ifdef SCIC_DEBUG_ENABLED
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#define MAX_STATE_TRANSITION_RECORD (256)
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/**
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* Debug code to record the state transitions for the phy object
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*/
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typedef struct SCIC_SDS_PHY_STATE_RECORD
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{
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SCI_BASE_OBSERVER_T base_state_observer;
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SCI_BASE_OBSERVER_T starting_state_observer;
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U16 index;
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U32 state_transition_table[MAX_STATE_TRANSITION_RECORD];
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} SCIC_SDS_PHY_STATE_RECORD_T;
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#endif // SCIC_DEBUG_ENABLED
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/**
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* @enum
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*
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* @brief This enumeration provides a named phy type for the state machine
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*/
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enum SCIC_SDS_PHY_PROTOCOL
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{
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/**
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* This is an unknown phy type since there is either nothing on the other
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* end or we have not detected the phy type as yet.
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*/
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SCIC_SDS_PHY_PROTOCOL_UNKNOWN,
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/**
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* This is a SAS PHY
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*/
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SCIC_SDS_PHY_PROTOCOL_SAS,
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/**
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* This is a SATA PHY
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*/
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SCIC_SDS_PHY_PROTOCOL_SATA,
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SCIC_SDS_MAX_PHY_PROTOCOLS
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};
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/**
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* @struct SCIC_SDS_PHY
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*
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* @brief This structure contains or references all of the data necessary to
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* represent the core phy object and SCU hardware protocol engine.
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*/
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typedef struct SCIC_SDS_PHY
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{
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SCI_BASE_PHY_T parent;
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/**
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* This field specifies the port object that owns/contains this phy.
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*/
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struct SCIC_SDS_PORT * owning_port;
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/**
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* This field indicates whether the phy supports 1.5 Gb/s, 3.0 Gb/s,
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* or 6.0 Gb/s operation.
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*/
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SCI_SAS_LINK_RATE max_negotiated_speed;
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/**
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* This member specifies the protocol being utilized on this phy. This
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* field contains a legitamite value once the PHY has link trained with
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* a remote phy.
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*/
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enum SCIC_SDS_PHY_PROTOCOL protocol;
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/**
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* This field specifies the index with which this phy is associated (0-3).
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*/
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U8 phy_index;
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/**
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* This member indicates if this particular PHY has received a BCN while
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* it had no port assignement. This BCN will be reported once the phy is
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* assigned to a port.
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*/
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BOOL bcn_received_while_port_unassigned;
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/**
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* This field indicates if this PHY is currently in the process of
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* link training (i.e. it has started OOB, but has yet to perform
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* IAF exchange/Signature FIS reception).
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*/
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BOOL is_in_link_training;
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union
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{
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struct
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{
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SCI_SAS_IDENTIFY_ADDRESS_FRAME_T identify_address_frame_buffer;
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} sas;
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struct
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{
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SATA_FIS_REG_D2H_T signature_fis_buffer;
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} sata;
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} phy_type;
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/**
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* This field contains a reference to the timer utilized in detecting
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* when a signature FIS timeout has occurred. The signature FIS is the
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* first FIS sent by an attached SATA device after OOB/SN.
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*/
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void * sata_timeout_timer;
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struct SCIC_SDS_PHY_STATE_HANDLER *state_handlers;
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SCI_BASE_STATE_MACHINE_T starting_substate_machine;
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#ifdef SCI_LOGGING
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SCI_BASE_STATE_MACHINE_LOGGER_T starting_substate_machine_logger;
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#endif
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#ifdef SCIC_DEBUG_ENABLED
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SCIC_SDS_PHY_STATE_RECORD_T state_record;
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#endif // SCIC_DEBUG_ENABLED
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/**
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* This field tracks how many errors of each type have been detected since
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* the last controller reset or counter clear. Note that these are only
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* for the error types that our driver needs to count manually. See
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* SCU_ERR_CNT_* values defined in scu_event_codes.h.
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*/
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U32 error_counter[SCU_ERR_CNT_MAX_INDEX];
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/**
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* This field is the pointer to the transport layer register for the SCU
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* hardware.
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*/
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SCU_TRANSPORT_LAYER_REGISTERS_T *transport_layer_registers;
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/**
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* This field points to the link layer register set within the SCU.
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*/
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SCU_LINK_LAYER_REGISTERS_T *link_layer_registers;
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} SCIC_SDS_PHY_T;
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typedef SCI_STATUS (*SCIC_SDS_PHY_EVENT_HANDLER_T)(SCIC_SDS_PHY_T *, U32);
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typedef SCI_STATUS (*SCIC_SDS_PHY_FRAME_HANDLER_T)(SCIC_SDS_PHY_T *, U32);
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typedef SCI_STATUS (*SCIC_SDS_PHY_POWER_HANDLER_T)(SCIC_SDS_PHY_T *);
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/**
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* @struct SCIC_SDS_PHY_STATE_HANDLER
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*/
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typedef struct SCIC_SDS_PHY_STATE_HANDLER
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{
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/**
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* This is the SCI_BASE_PHY object state handlers.
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*/
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SCI_BASE_PHY_STATE_HANDLER_T parent;
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/**
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* The state handler for unsolicited frames received from the SCU hardware.
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*/
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SCIC_SDS_PHY_FRAME_HANDLER_T frame_handler;
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/**
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* The state handler for events received from the SCU hardware.
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*/
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SCIC_SDS_PHY_EVENT_HANDLER_T event_handler;
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/**
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* The state handler for staggered spinup.
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*/
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SCIC_SDS_PHY_POWER_HANDLER_T consume_power_handler;
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} SCIC_SDS_PHY_STATE_HANDLER_T;
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extern SCIC_SDS_PHY_STATE_HANDLER_T scic_sds_phy_state_handler_table[];
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extern SCI_BASE_STATE_T scic_sds_phy_state_table[];
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extern SCI_BASE_STATE_T scic_sds_phy_starting_substates[];
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extern SCIC_SDS_PHY_STATE_HANDLER_T
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scic_sds_phy_starting_substate_handler_table[];
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/**
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* This macro returns the phy index for the specified phy
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*/
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#define scic_sds_phy_get_index(phy) \
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((phy)->phy_index)
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/**
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* @brief This macro returns the controller for this phy
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*/
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#define scic_sds_phy_get_controller(phy) \
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(scic_sds_port_get_controller((phy)->owning_port))
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/**
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* @brief This macro returns the state machine for the base phy
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*/
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#define scic_sds_phy_get_base_state_machine(phy) \
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(&(phy)->parent.state_machine)
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/**
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* @brief This macro returns the starting substate machine for
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* this phy
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*/
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#define scic_sds_phy_get_starting_substate_machine(phy) \
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(&(phy)->starting_substate_machine)
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/**
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* @brief This macro sets the state handlers for this phy object
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*/
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#define scic_sds_phy_set_state_handlers(phy, handlers) \
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((phy)->state_handlers = (handlers))
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/**
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* This macro set the base state handlers for the phy object.
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*/
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#define scic_sds_phy_set_base_state_handlers(phy, state_id) \
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scic_sds_phy_set_state_handlers( \
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(phy), \
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&scic_sds_phy_state_handler_table[(state_id)] \
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)
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/**
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* This macro returns TRUE if the current base state for this phy is
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* SCI_BASE_PHY_STATE_READY
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*/
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#define scic_sds_phy_is_ready(phy) \
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( \
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SCI_BASE_PHY_STATE_READY \
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== sci_base_state_machine_get_state( \
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scic_sds_phy_get_base_state_machine(phy) \
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) \
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)
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// ---------------------------------------------------------------------------
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U32 scic_sds_phy_get_object_size(void);
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U32 scic_sds_phy_get_min_timer_count(void);
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U32 scic_sds_phy_get_max_timer_count(void);
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// ---------------------------------------------------------------------------
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void scic_sds_phy_construct(
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struct SCIC_SDS_PHY *this_phy,
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struct SCIC_SDS_PORT *owning_port,
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U8 phy_index
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);
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SCI_PORT_HANDLE_T scic_sds_phy_get_port(
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SCIC_SDS_PHY_T *this_phy
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);
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void scic_sds_phy_set_port(
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struct SCIC_SDS_PHY *this_phy,
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struct SCIC_SDS_PORT *owning_port
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);
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SCI_STATUS scic_sds_phy_initialize(
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SCIC_SDS_PHY_T *this_phy,
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void *transport_layer_registers,
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SCU_LINK_LAYER_REGISTERS_T *link_layer_registers
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);
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SCI_STATUS scic_sds_phy_reset(
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SCIC_SDS_PHY_T * this_phy
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);
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void scic_sds_phy_sata_timeout(
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SCI_OBJECT_HANDLE_T cookie
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);
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// ---------------------------------------------------------------------------
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void scic_sds_phy_suspend(
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struct SCIC_SDS_PHY *this_phy
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);
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void scic_sds_phy_resume(
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struct SCIC_SDS_PHY *this_phy
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);
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void scic_sds_phy_setup_transport(
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struct SCIC_SDS_PHY * this_phy,
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U32 device_id
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);
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// ---------------------------------------------------------------------------
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SCI_STATUS scic_sds_phy_event_handler(
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SCIC_SDS_PHY_T *this_phy,
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U32 event_code
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);
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SCI_STATUS scic_sds_phy_frame_handler(
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SCIC_SDS_PHY_T *this_phy,
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U32 frame_index
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);
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SCI_STATUS scic_sds_phy_consume_power_handler(
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SCIC_SDS_PHY_T *this_phy
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);
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void scic_sds_phy_get_sas_address(
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SCIC_SDS_PHY_T *this_phy,
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SCI_SAS_ADDRESS_T *sas_address
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);
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void scic_sds_phy_get_attached_sas_address(
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SCIC_SDS_PHY_T *this_phy,
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SCI_SAS_ADDRESS_T *sas_address
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);
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void scic_sds_phy_get_protocols(
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SCIC_SDS_PHY_T *this_phy,
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SCI_SAS_IDENTIFY_ADDRESS_FRAME_PROTOCOLS_T * protocols
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);
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void scic_sds_phy_get_attached_phy_protocols(
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SCIC_SDS_PHY_T *this_phy,
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SCI_SAS_IDENTIFY_ADDRESS_FRAME_PROTOCOLS_T * protocols
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);
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//****************************************************************************-
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//* SCIC SDS PHY Handler Methods
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//****************************************************************************-
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SCI_STATUS scic_sds_phy_default_start_handler(
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SCI_BASE_PHY_T *phy
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);
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SCI_STATUS scic_sds_phy_default_stop_handler(
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SCI_BASE_PHY_T *phy
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);
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SCI_STATUS scic_sds_phy_default_reset_handler(
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SCI_BASE_PHY_T * phy
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);
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SCI_STATUS scic_sds_phy_default_destroy_handler(
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SCI_BASE_PHY_T *phy
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);
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SCI_STATUS scic_sds_phy_default_frame_handler(
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SCIC_SDS_PHY_T *phy,
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U32 frame_index
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);
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SCI_STATUS scic_sds_phy_default_event_handler(
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SCIC_SDS_PHY_T *phy,
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U32 evnet_code
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);
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SCI_STATUS scic_sds_phy_default_consume_power_handler(
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SCIC_SDS_PHY_T *phy
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);
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void scic_sds_phy_release_resource(
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struct SCIC_SDS_CONTROLLER * controller,
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struct SCIC_SDS_PHY * phy
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);
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void scic_sds_phy_restart_starting_state(
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struct SCIC_SDS_PHY * this_phy
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);
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#ifdef __cplusplus
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}
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#endif // __cplusplus
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#endif // _SCIC_SDS_PHY_H_
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