bc5676e30c
GetSeconds(). Instead, use CRTR register shifted right 15. This gives us a range of 32 seconds we can do for timeout. Shift to using == rather than < or > for calculating the timeout, since if we can't read the ST_CTRT register twice in a second we have even bigger problems to worry about, and == deals with the 'wrap' issue. This lets me type at the boot2 prompt again! Woo Hoo! Bogusness noticed by: tisco Pointy Hat to: That silly imp guy
67 lines
2.4 KiB
C
67 lines
2.4 KiB
C
/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _AT91RM9200_LOWLEVEL_H_
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#define _AT91RM9200_LOWLEVEL_H_
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/* default system config parameters */
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#define SDRAM_BASE 0x20000000
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#ifdef BOOT_KB920X
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/* The following divisor sets PLLA frequency: e.g. 10/5 * 90 = 180MHz */
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#define OSC_MAIN_FREQ_DIV 5 /* for 10MHz osc */
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#define SDRAM_WIDTH AT91C_SDRC_DBW_16_BITS
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typedef unsigned short sdram_size_t;
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#define OSC_MAIN_MULT 90
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#endif
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#ifdef BOOT_BWCT
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/* The following divisor sets PLLA frequency: e.g. 16/4 * 45 = 180MHz */
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#define OSC_MAIN_FREQ_DIV 4 /* for 16MHz osc */
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#define SDRAM_WIDTH AT91C_SDRC_DBW_32_BITS
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typedef unsigned int sdram_size_t;
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#define OSC_MAIN_MULT 45
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#endif
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#ifdef BOOT_TSC
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/* The following divisor sets PLLA frequency: e.g. 16/4 * 45 = 180MHz */
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#define OSC_MAIN_FREQ_DIV 4 /* for 16MHz osc */
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#define SDRAM_WIDTH AT91C_SDRC_DBW_32_BITS
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typedef unsigned int sdram_size_t;
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#define OSC_MAIN_MULT 45
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#endif
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/* Master clock frequency at power-up */
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#define AT91C_MASTER_CLOCK 60000000
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/* #define GetSeconds() (AT91C_BASE_RTC->RTC_TIMR & AT91C_RTC_SEC) */
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#define GetSeconds() (AT91C_BASE_ST->ST_CRTR >> 15)
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extern void _init(void);
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#endif /* _AT91RM9200_LOWLEVEL_H_ */
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