a8e715d21b
Add a refcount for posted WQEs to avoid a race between post WQE and FW command flows. MFC after: 1 week Sponsored by: NVIDIA Networking
174 lines
6.9 KiB
C
174 lines
6.9 KiB
C
/*-
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* Copyright (c) 2016 Mellanox Technologies. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __MLX5_EN_RL_H__
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#define __MLX5_EN_RL_H__
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#include <sys/param.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sx.h>
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#include <sys/proc.h>
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#include <sys/condvar.h>
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#include <sys/interrupt.h>
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#include <sys/unistd.h>
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#include <sys/queue.h>
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#define MLX5E_RL_MAX_WORKERS 128 /* limited by Toeplitz hash */
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#define MLX5E_RL_MAX_TX_RATES (64 * 1024) /* software limit */
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#define MLX5E_RL_DEF_SQ_PER_WORKER (12 * 1024) /* software limit */
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#define MLX5E_RL_MAX_SQS (120 * 1024) /* software limit */
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#define MLX5E_RL_TX_COAL_USEC_DEFAULT 32
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#define MLX5E_RL_TX_COAL_PKTS_DEFAULT 4
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#define MLX5E_RL_TX_COAL_MODE_DEFAULT 0
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#define MLX5E_RL_TX_COMP_FACT_DEFAULT 1
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#define MLX5E_RL_WORKER_LOCK(rlw) mtx_lock(&(rlw)->mtx)
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#define MLX5E_RL_WORKER_UNLOCK(rlw) mtx_unlock(&(rlw)->mtx)
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#define MLX5E_RL_RLOCK(rl) sx_slock(&(rl)->rl_sxlock)
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#define MLX5E_RL_RUNLOCK(rl) sx_sunlock(&(rl)->rl_sxlock)
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#define MLX5E_RL_WLOCK(rl) sx_xlock(&(rl)->rl_sxlock)
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#define MLX5E_RL_WUNLOCK(rl) sx_xunlock(&(rl)->rl_sxlock)
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#define MLX5E_RL_PARAMS(m) \
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m(+1, u64, tx_queue_size, "tx_queue_size", "Default send queue size") \
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m(+1, u64, tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining TX packets") \
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m(+1, u64, tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of TX packets to join") \
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m(+1, u64, tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \
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m(+1, u64, tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \
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m(+1, u64, tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \
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m(+1, u64, tx_worker_threads_max, "tx_worker_threads_max", "Max number of TX worker threads") \
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m(+1, u64, tx_worker_threads_def, "tx_worker_threads_def", "Default number of TX worker threads") \
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m(+1, u64, tx_channels_per_worker_max, "tx_channels_per_worker_max", "Max number of TX channels per worker") \
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m(+1, u64, tx_channels_per_worker_def, "tx_channels_per_worker_def", "Default number of TX channels per worker") \
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m(+1, u64, tx_rates_max, "tx_rates_max", "Max number of TX rates") \
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m(+1, u64, tx_rates_def, "tx_rates_def", "Default number of TX rates") \
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m(+1, u64, tx_limit_min, "tx_limit_min", "Minimum TX rate in bits/s") \
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m(+1, u64, tx_limit_max, "tx_limit_max", "Maximum TX rate in bits/s") \
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m(+1, u64, tx_burst_size, "tx_burst_size", "Current burst size in number of packets. A value of zero means use firmware default.") \
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m(+1, u64, tx_burst_size_max, "tx_burst_size_max", "Maximum burst size in number of packets") \
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m(+1, u64, tx_burst_size_min, "tx_burst_size_min", "Minimum burst size in number of packets")
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#define MLX5E_RL_PARAMS_NUM (0 MLX5E_RL_PARAMS(MLX5E_STATS_COUNT))
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#define MLX5E_RL_STATS(m) \
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m(+1, u64, tx_allocate_resource_failure, "tx_allocate_resource_failure", "Number of times firmware resource allocation failed") \
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m(+1, u64, tx_add_new_rate_failure, "tx_add_new_rate_failure", "Number of times adding a new firmware rate failed") \
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m(+1, u64, tx_modify_rate_failure, "tx_modify_rate_failure", "Number of times modifying a firmware rate failed") \
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m(+1, u64, tx_active_connections, "tx_active_connections", "Number of active connections") \
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m(+1, u64, tx_open_queues, "tx_open_queues", "Number of open TX queues") \
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m(+1, u64, tx_available_resource_failure, "tx_available_resource_failure", "Number of times TX resources were not available")
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#define MLX5E_RL_STATS_NUM (0 MLX5E_RL_STATS(MLX5E_STATS_COUNT))
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#define MLX5E_RL_TABLE_PARAMS(m) \
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m(+1, u64, tx_limit_add, "tx_limit_add", "Add TX rate limit in bits/s to empty slot") \
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m(+1, u64, tx_limit_clr, "tx_limit_clr", "Clear all TX rates in table") \
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m(+1, u64, tx_allowed_deviation, "tx_allowed_deviation", "Relative rate deviation allowed in 1/1000") \
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m(+1, u64, tx_allowed_deviation_min, "tx_allowed_deviation_min", "Minimum allowed rate deviation in 1/1000") \
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m(+1, u64, tx_allowed_deviation_max, "tx_allowed_deviation_max", "Maximum allowed rate deviation in 1/1000")
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#define MLX5E_RL_TABLE_PARAMS_NUM (0 MLX5E_RL_TABLE_PARAMS(MLX5E_STATS_COUNT))
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#define MLX5E_RL_PARAMS_INDEX(n) \
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(__offsetof(struct mlx5e_rl_params, n) / sizeof(uint64_t))
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struct mlx5e_priv;
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/* Indicates channel's state */
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enum {
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MLX5E_RL_ST_FREE,
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MLX5E_RL_ST_USED,
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MLX5E_RL_ST_MODIFY,
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MLX5E_RL_ST_DESTROY,
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};
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struct mlx5e_rl_stats {
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u64 arg [0];
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MLX5E_RL_STATS(MLX5E_STATS_VAR)
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};
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struct mlx5e_rl_params {
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u64 arg [0];
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MLX5E_RL_PARAMS(MLX5E_STATS_VAR)
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u64 table_arg [0];
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MLX5E_RL_TABLE_PARAMS(MLX5E_STATS_VAR)
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};
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struct mlx5e_rl_channel_param {
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struct mlx5e_sq_param sq;
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struct mlx5e_cq_param cq;
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};
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struct mlx5e_rl_channel {
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struct m_snd_tag tag;
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STAILQ_ENTRY(mlx5e_rl_channel) entry;
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struct mlx5e_sq * volatile sq;
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struct mlx5e_rl_worker *worker;
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uint64_t new_rate;
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uint64_t init_rate;
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uint64_t last_rate;
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uint32_t refcount;
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uint16_t last_burst;
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uint16_t state;
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};
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struct mlx5e_rl_worker {
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struct mtx mtx;
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struct cv cv;
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STAILQ_HEAD(, mlx5e_rl_channel) index_list_head;
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STAILQ_HEAD(, mlx5e_rl_channel) process_head;
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struct mlx5e_priv *priv;
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struct mlx5e_rl_channel *channels;
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unsigned worker_done;
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};
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struct mlx5e_rl_priv_data {
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struct sx rl_sxlock;
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struct sysctl_ctx_list ctx;
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struct mlx5e_rl_channel_param chan_param;
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struct mlx5e_rl_params param;
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struct mlx5e_rl_stats stats;
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struct mlx5e_rl_worker *workers;
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struct mlx5e_priv *priv;
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uint64_t *rate_limit_table;
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unsigned opened;
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uint32_t tisn;
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};
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int mlx5e_rl_init(struct mlx5e_priv *priv);
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void mlx5e_rl_cleanup(struct mlx5e_priv *priv);
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void mlx5e_rl_refresh_sq_inline(struct mlx5e_rl_priv_data *rl);
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if_snd_tag_alloc_t mlx5e_rl_snd_tag_alloc;
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#endif /* __MLX5_EN_RL_H__ */
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