7695ced633
If firmware_get() fails to find a loaded firmware image, it searches for candidate KLDs to load. It will search for a KLD containing a module with the same name as the requested image, and failing that, will load a KLD with the same basename as the requested image. The module name given by fw_stub.awk is simply "<mangled KLD name>_fw". QAT firmware modules contain two images, neither of which match either of the names used during lookup, so automatic loading of firmware images after mountroot does not work. Work around this by using the same string for the first image name and for the KLD basename. MFC after: 3 days Sponsored by: Rubicon Communications, LLC (Netgate)
202 lines
7.7 KiB
C
202 lines
7.7 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
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/* $NetBSD: qat_d15xxreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */
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/*
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* Copyright (c) 2019 Internet Initiative Japan, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright(c) 2014 Intel Corporation.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef _DEV_PCI_QAT_D15XXREG_H_
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#define _DEV_PCI_QAT_D15XXREG_H_
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/* Max number of accelerators and engines */
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#define MAX_ACCEL_D15XX 5
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#define MAX_AE_D15XX 10
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/* PCIe BAR index */
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#define BAR_SRAM_ID_D15XX 0
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#define BAR_PMISC_ID_D15XX 1
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#define BAR_ETR_ID_D15XX 2
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/* BAR PMISC sub-regions */
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#define AE_OFFSET_D15XX 0x20000
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#define AE_LOCAL_OFFSET_D15XX 0x20800
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#define CAP_GLOBAL_OFFSET_D15XX 0x30000
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#define SOFTSTRAP_REG_D15XX 0x2EC
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#define SOFTSTRAP_SS_POWERGATE_CY_D15XX __BIT(23)
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#define SOFTSTRAP_SS_POWERGATE_PKE_D15XX __BIT(24)
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#define ACCEL_REG_OFFSET_D15XX 16
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#define ACCEL_MASK_D15XX 0x1F
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#define AE_MASK_D15XX 0x3FF
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#define SMIAPF0_D15XX 0x3A028
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#define SMIAPF1_D15XX 0x3A030
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#define SMIA0_MASK_D15XX 0xFFFF
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#define SMIA1_MASK_D15XX 0x1
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/* Error detection and correction */
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#define AE_CTX_ENABLES_D15XX(i) ((i) * 0x1000 + 0x20818)
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#define AE_MISC_CONTROL_D15XX(i) ((i) * 0x1000 + 0x20960)
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#define ENABLE_AE_ECC_ERR_D15XX __BIT(28)
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#define ENABLE_AE_ECC_PARITY_CORR_D15XX (__BIT(24) | __BIT(12))
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#define ERRSSMSH_EN_D15XX __BIT(3)
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/* BIT(2) enables the logging of push/pull data errors. */
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#define PPERR_EN_D15XX (__BIT(2))
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/* Mask for VF2PF interrupts */
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#define VF2PF1_16_D15XX (0xFFFF << 9)
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#define ERRSOU3_VF2PF_D15XX(errsou3) (((errsou3) & 0x01FFFE00) >> 9)
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#define ERRMSK3_VF2PF_D15XX(vf_mask) (((vf_mask) & 0xFFFF) << 9)
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/* Masks for correctable error interrupts. */
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#define ERRMSK0_CERR_D15XX (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
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#define ERRMSK1_CERR_D15XX (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
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#define ERRMSK3_CERR_D15XX (__BIT(7))
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#define ERRMSK4_CERR_D15XX (__BIT(8) | __BIT(0))
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#define ERRMSK5_CERR_D15XX (0)
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/* Masks for uncorrectable error interrupts. */
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#define ERRMSK0_UERR_D15XX (__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
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#define ERRMSK1_UERR_D15XX (__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
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#define ERRMSK3_UERR_D15XX (__BIT(8) | __BIT(6) | __BIT(5) | __BIT(4) | \
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__BIT(3) | __BIT(2) | __BIT(0))
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#define ERRMSK4_UERR_D15XX (__BIT(9) | __BIT(1))
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#define ERRMSK5_UERR_D15XX (__BIT(18) | __BIT(17) | __BIT(16))
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/* RI CPP control */
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#define RICPPINTCTL_D15XX (0x3A000 + 0x110)
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/*
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* BIT(2) enables error detection and reporting on the RI Parity Error.
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* BIT(1) enables error detection and reporting on the RI CPP Pull interface.
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* BIT(0) enables error detection and reporting on the RI CPP Push interface.
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*/
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#define RICPP_EN_D15XX (__BIT(2) | __BIT(1) | __BIT(0))
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/* TI CPP control */
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#define TICPPINTCTL_D15XX (0x3A400 + 0x138)
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/*
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* BIT(3) enables error detection and reporting on the ETR Parity Error.
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* BIT(2) enables error detection and reporting on the TI Parity Error.
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* BIT(1) enables error detection and reporting on the TI CPP Pull interface.
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* BIT(0) enables error detection and reporting on the TI CPP Push interface.
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*/
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#define TICPP_EN_D15XX \
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(__BIT(4) | __BIT(3) | __BIT(2) | __BIT(1) | __BIT(0))
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/* CFC Uncorrectable Errors */
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#define CPP_CFC_ERR_CTRL_D15XX (0x30000 + 0xC00)
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/*
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* BIT(1) enables interrupt.
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* BIT(0) enables detecting and logging of push/pull data errors.
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*/
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#define CPP_CFC_UE_D15XX (__BIT(1) | __BIT(0))
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/* Correctable SecureRAM Error Reg */
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#define SECRAMCERR_D15XX (0x3AC00 + 0x00)
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/* BIT(3) enables fixing and logging of correctable errors. */
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#define SECRAM_CERR_D15XX (__BIT(3))
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/* Uncorrectable SecureRAM Error Reg */
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/*
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* BIT(17) enables interrupt.
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* BIT(3) enables detecting and logging of uncorrectable errors.
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*/
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#define SECRAM_UERR_D15XX (__BIT(17) | __BIT(3))
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/* Miscellaneous Memory Target Errors Register */
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/*
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* BIT(3) enables detecting and logging push/pull data errors.
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* BIT(2) enables interrupt.
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*/
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#define TGT_UERR_D15XX (__BIT(3) | __BIT(2))
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#define SLICEPWRDOWN_D15XX(i) ((i) * 0x4000 + 0x2C)
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/* Enabling PKE4-PKE0. */
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#define MMP_PWR_UP_MSK_D15XX \
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(__BIT(20) | __BIT(19) | __BIT(18) | __BIT(17) | __BIT(16))
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/* CPM Uncorrectable Errors */
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#define INTMASKSSM_D15XX(i) ((i) * 0x4000 + 0x0)
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/* Disabling interrupts for correctable errors. */
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#define INTMASKSSM_UERR_D15XX \
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(__BIT(11) | __BIT(9) | __BIT(7) | __BIT(5) | __BIT(3) | __BIT(1))
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/* MMP */
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/* BIT(3) enables correction. */
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#define CERRSSMMMP_EN_D15XX (__BIT(3))
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/* BIT(3) enables logging. */
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#define UERRSSMMMP_EN_D15XX (__BIT(3))
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/* ETR */
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#define ETR_MAX_BANKS_D15XX 16
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#define ETR_TX_RX_GAP_D15XX 8
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#define ETR_TX_RINGS_MASK_D15XX 0xFF
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#define ETR_BUNDLE_SIZE_D15XX 0x1000
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/* AE firmware */
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#define AE_FW_PROD_TYPE_D15XX 0x01000000
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#define AE_FW_MOF_NAME_D15XX "qat_d15xxfw"
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#define AE_FW_MMP_NAME_D15XX "qat_d15xx_mmp"
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#define AE_FW_UOF_NAME_D15XX "icp_qat_ae.suof"
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/* Clock frequency */
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#define CLOCK_PER_SEC_D15XX (685 * 1000000 / 16)
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#endif
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