583 lines
12 KiB
ArmAsm
583 lines
12 KiB
ArmAsm
/* $FreeBSD$ */
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/* Do not modify. This file is auto-generated from armv4-mont.pl. */
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#include "arm_arch.h"
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.text
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.code 32
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#if __ARM_MAX_ARCH__>=7
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.align 5
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.LOPENSSL_armcap:
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.word OPENSSL_armcap_P-bn_mul_mont
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#endif
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.global bn_mul_mont
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.type bn_mul_mont,%function
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.align 5
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bn_mul_mont:
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ldr ip,[sp,#4] @ load num
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stmdb sp!,{r0,r2} @ sp points at argument block
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#if __ARM_MAX_ARCH__>=7
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tst ip,#7
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bne .Lialu
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adr r0,bn_mul_mont
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ldr r2,.LOPENSSL_armcap
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ldr r0,[r0,r2]
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tst r0,#1 @ NEON available?
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ldmia sp, {r0,r2}
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beq .Lialu
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add sp,sp,#8
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b bn_mul8x_mont_neon
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.align 4
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.Lialu:
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#endif
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cmp ip,#2
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mov r0,ip @ load num
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movlt r0,#0
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addlt sp,sp,#2*4
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blt .Labrt
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stmdb sp!,{r4-r12,lr} @ save 10 registers
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mov r0,r0,lsl#2 @ rescale r0 for byte count
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sub sp,sp,r0 @ alloca(4*num)
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sub sp,sp,#4 @ +extra dword
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sub r0,r0,#4 @ "num=num-1"
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add r4,r2,r0 @ &bp[num-1]
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add r0,sp,r0 @ r0 to point at &tp[num-1]
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ldr r8,[r0,#14*4] @ &n0
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ldr r2,[r2] @ bp[0]
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ldr r5,[r1],#4 @ ap[0],ap++
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ldr r6,[r3],#4 @ np[0],np++
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ldr r8,[r8] @ *n0
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str r4,[r0,#15*4] @ save &bp[num]
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umull r10,r11,r5,r2 @ ap[0]*bp[0]
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str r8,[r0,#14*4] @ save n0 value
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mul r8,r10,r8 @ "tp[0]"*n0
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mov r12,#0
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umlal r10,r12,r6,r8 @ np[0]*n0+"t[0]"
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mov r4,sp
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.L1st:
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ldr r5,[r1],#4 @ ap[j],ap++
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mov r10,r11
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ldr r6,[r3],#4 @ np[j],np++
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mov r11,#0
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umlal r10,r11,r5,r2 @ ap[j]*bp[0]
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mov r14,#0
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umlal r12,r14,r6,r8 @ np[j]*n0
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adds r12,r12,r10
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str r12,[r4],#4 @ tp[j-1]=,tp++
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adc r12,r14,#0
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cmp r4,r0
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bne .L1st
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adds r12,r12,r11
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ldr r4,[r0,#13*4] @ restore bp
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mov r14,#0
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ldr r8,[r0,#14*4] @ restore n0
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adc r14,r14,#0
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str r12,[r0] @ tp[num-1]=
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str r14,[r0,#4] @ tp[num]=
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.Louter:
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sub r7,r0,sp @ "original" r0-1 value
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sub r1,r1,r7 @ "rewind" ap to &ap[1]
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ldr r2,[r4,#4]! @ *(++bp)
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sub r3,r3,r7 @ "rewind" np to &np[1]
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ldr r5,[r1,#-4] @ ap[0]
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ldr r10,[sp] @ tp[0]
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ldr r6,[r3,#-4] @ np[0]
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ldr r7,[sp,#4] @ tp[1]
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mov r11,#0
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umlal r10,r11,r5,r2 @ ap[0]*bp[i]+tp[0]
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str r4,[r0,#13*4] @ save bp
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mul r8,r10,r8
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mov r12,#0
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umlal r10,r12,r6,r8 @ np[0]*n0+"tp[0]"
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mov r4,sp
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.Linner:
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ldr r5,[r1],#4 @ ap[j],ap++
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adds r10,r11,r7 @ +=tp[j]
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ldr r6,[r3],#4 @ np[j],np++
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mov r11,#0
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umlal r10,r11,r5,r2 @ ap[j]*bp[i]
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mov r14,#0
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umlal r12,r14,r6,r8 @ np[j]*n0
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adc r11,r11,#0
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ldr r7,[r4,#8] @ tp[j+1]
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adds r12,r12,r10
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str r12,[r4],#4 @ tp[j-1]=,tp++
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adc r12,r14,#0
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cmp r4,r0
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bne .Linner
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adds r12,r12,r11
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mov r14,#0
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ldr r4,[r0,#13*4] @ restore bp
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adc r14,r14,#0
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ldr r8,[r0,#14*4] @ restore n0
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adds r12,r12,r7
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ldr r7,[r0,#15*4] @ restore &bp[num]
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adc r14,r14,#0
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str r12,[r0] @ tp[num-1]=
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str r14,[r0,#4] @ tp[num]=
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cmp r4,r7
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bne .Louter
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ldr r2,[r0,#12*4] @ pull rp
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add r0,r0,#4 @ r0 to point at &tp[num]
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sub r5,r0,sp @ "original" num value
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mov r4,sp @ "rewind" r4
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mov r1,r4 @ "borrow" r1
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sub r3,r3,r5 @ "rewind" r3 to &np[0]
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subs r7,r7,r7 @ "clear" carry flag
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.Lsub: ldr r7,[r4],#4
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ldr r6,[r3],#4
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sbcs r7,r7,r6 @ tp[j]-np[j]
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str r7,[r2],#4 @ rp[j]=
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teq r4,r0 @ preserve carry
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bne .Lsub
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sbcs r14,r14,#0 @ upmost carry
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mov r4,sp @ "rewind" r4
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sub r2,r2,r5 @ "rewind" r2
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and r1,r4,r14
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bic r3,r2,r14
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orr r1,r1,r3 @ ap=borrow?tp:rp
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.Lcopy: ldr r7,[r1],#4 @ copy or in-place refresh
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str sp,[r4],#4 @ zap tp
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str r7,[r2],#4
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cmp r4,r0
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bne .Lcopy
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add sp,r0,#4 @ skip over tp[num+1]
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ldmia sp!,{r4-r12,lr} @ restore registers
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add sp,sp,#2*4 @ skip over {r0,r2}
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mov r0,#1
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.Labrt:
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#if __ARM_ARCH__>=5
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bx lr @ .word 0xe12fff1e
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#else
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tst lr,#1
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moveq pc,lr @ be binary compatible with V4, yet
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.word 0xe12fff1e @ interoperable with Thumb ISA:-)
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#endif
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.size bn_mul_mont,.-bn_mul_mont
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#if __ARM_MAX_ARCH__>=7
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.arch armv7-a
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.fpu neon
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.type bn_mul8x_mont_neon,%function
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.align 5
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bn_mul8x_mont_neon:
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mov ip,sp
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stmdb sp!,{r4-r11}
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vstmdb sp!,{d8-d15} @ ABI specification says so
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ldmia ip,{r4-r5} @ load rest of parameter block
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sub r7,sp,#16
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vld1.32 {d28[0]}, [r2,:32]!
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sub r7,r7,r5,lsl#4
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vld1.32 {d0-d3}, [r1]! @ can't specify :32 :-(
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and r7,r7,#-64
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vld1.32 {d30[0]}, [r4,:32]
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mov sp,r7 @ alloca
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veor d8,d8,d8
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subs r8,r5,#8
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vzip.16 d28,d8
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vmull.u32 q6,d28,d0[0]
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vmull.u32 q7,d28,d0[1]
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vmull.u32 q8,d28,d1[0]
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vshl.i64 d10,d13,#16
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vmull.u32 q9,d28,d1[1]
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vadd.u64 d10,d10,d12
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veor d8,d8,d8
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vmul.u32 d29,d10,d30
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vmull.u32 q10,d28,d2[0]
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vld1.32 {d4-d7}, [r3]!
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vmull.u32 q11,d28,d2[1]
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vmull.u32 q12,d28,d3[0]
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vzip.16 d29,d8
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vmull.u32 q13,d28,d3[1]
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bne .LNEON_1st
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@ special case for num=8, everything is in register bank...
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vmlal.u32 q6,d29,d4[0]
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sub r9,r5,#1
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vmlal.u32 q7,d29,d4[1]
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vmlal.u32 q8,d29,d5[0]
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vmlal.u32 q9,d29,d5[1]
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vmlal.u32 q10,d29,d6[0]
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vmov q5,q6
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vmlal.u32 q11,d29,d6[1]
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vmov q6,q7
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vmlal.u32 q12,d29,d7[0]
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vmov q7,q8
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vmlal.u32 q13,d29,d7[1]
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vmov q8,q9
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vmov q9,q10
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vshr.u64 d10,d10,#16
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vmov q10,q11
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vmov q11,q12
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vadd.u64 d10,d10,d11
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vmov q12,q13
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veor q13,q13
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vshr.u64 d10,d10,#16
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b .LNEON_outer8
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.align 4
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.LNEON_outer8:
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vld1.32 {d28[0]}, [r2,:32]!
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veor d8,d8,d8
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vzip.16 d28,d8
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vadd.u64 d12,d12,d10
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vmlal.u32 q6,d28,d0[0]
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vmlal.u32 q7,d28,d0[1]
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vmlal.u32 q8,d28,d1[0]
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vshl.i64 d10,d13,#16
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vmlal.u32 q9,d28,d1[1]
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vadd.u64 d10,d10,d12
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veor d8,d8,d8
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subs r9,r9,#1
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vmul.u32 d29,d10,d30
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vmlal.u32 q10,d28,d2[0]
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vmlal.u32 q11,d28,d2[1]
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vmlal.u32 q12,d28,d3[0]
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vzip.16 d29,d8
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vmlal.u32 q13,d28,d3[1]
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vmlal.u32 q6,d29,d4[0]
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vmlal.u32 q7,d29,d4[1]
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vmlal.u32 q8,d29,d5[0]
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vmlal.u32 q9,d29,d5[1]
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vmlal.u32 q10,d29,d6[0]
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vmov q5,q6
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vmlal.u32 q11,d29,d6[1]
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vmov q6,q7
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vmlal.u32 q12,d29,d7[0]
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vmov q7,q8
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vmlal.u32 q13,d29,d7[1]
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vmov q8,q9
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vmov q9,q10
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vshr.u64 d10,d10,#16
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vmov q10,q11
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vmov q11,q12
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vadd.u64 d10,d10,d11
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vmov q12,q13
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veor q13,q13
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vshr.u64 d10,d10,#16
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bne .LNEON_outer8
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vadd.u64 d12,d12,d10
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mov r7,sp
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vshr.u64 d10,d12,#16
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mov r8,r5
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vadd.u64 d13,d13,d10
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add r6,sp,#16
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vshr.u64 d10,d13,#16
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vzip.16 d12,d13
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b .LNEON_tail2
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.align 4
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.LNEON_1st:
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vmlal.u32 q6,d29,d4[0]
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vld1.32 {d0-d3}, [r1]!
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vmlal.u32 q7,d29,d4[1]
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subs r8,r8,#8
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vmlal.u32 q8,d29,d5[0]
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vmlal.u32 q9,d29,d5[1]
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vmlal.u32 q10,d29,d6[0]
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vld1.32 {d4-d5}, [r3]!
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vmlal.u32 q11,d29,d6[1]
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vst1.64 {q6-q7}, [r7,:256]!
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vmlal.u32 q12,d29,d7[0]
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vmlal.u32 q13,d29,d7[1]
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vst1.64 {q8-q9}, [r7,:256]!
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vmull.u32 q6,d28,d0[0]
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vld1.32 {d6-d7}, [r3]!
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vmull.u32 q7,d28,d0[1]
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vst1.64 {q10-q11}, [r7,:256]!
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vmull.u32 q8,d28,d1[0]
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vmull.u32 q9,d28,d1[1]
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vst1.64 {q12-q13}, [r7,:256]!
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vmull.u32 q10,d28,d2[0]
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vmull.u32 q11,d28,d2[1]
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vmull.u32 q12,d28,d3[0]
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vmull.u32 q13,d28,d3[1]
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bne .LNEON_1st
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vmlal.u32 q6,d29,d4[0]
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add r6,sp,#16
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vmlal.u32 q7,d29,d4[1]
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sub r1,r1,r5,lsl#2 @ rewind r1
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vmlal.u32 q8,d29,d5[0]
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vld1.64 {q5}, [sp,:128]
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vmlal.u32 q9,d29,d5[1]
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sub r9,r5,#1
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vmlal.u32 q10,d29,d6[0]
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vst1.64 {q6-q7}, [r7,:256]!
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vmlal.u32 q11,d29,d6[1]
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vshr.u64 d10,d10,#16
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vld1.64 {q6}, [r6, :128]!
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vmlal.u32 q12,d29,d7[0]
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vst1.64 {q8-q9}, [r7,:256]!
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vmlal.u32 q13,d29,d7[1]
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vst1.64 {q10-q11}, [r7,:256]!
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vadd.u64 d10,d10,d11
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veor q4,q4,q4
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vst1.64 {q12-q13}, [r7,:256]!
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vld1.64 {q7-q8}, [r6, :256]!
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vst1.64 {q4}, [r7,:128]
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vshr.u64 d10,d10,#16
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b .LNEON_outer
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.align 4
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.LNEON_outer:
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vld1.32 {d28[0]}, [r2,:32]!
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sub r3,r3,r5,lsl#2 @ rewind r3
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vld1.32 {d0-d3}, [r1]!
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veor d8,d8,d8
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mov r7,sp
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vzip.16 d28,d8
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sub r8,r5,#8
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vadd.u64 d12,d12,d10
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vmlal.u32 q6,d28,d0[0]
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vld1.64 {q9-q10},[r6,:256]!
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vmlal.u32 q7,d28,d0[1]
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vmlal.u32 q8,d28,d1[0]
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vld1.64 {q11-q12},[r6,:256]!
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vmlal.u32 q9,d28,d1[1]
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vshl.i64 d10,d13,#16
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veor d8,d8,d8
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vadd.u64 d10,d10,d12
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vld1.64 {q13},[r6,:128]!
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vmul.u32 d29,d10,d30
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vmlal.u32 q10,d28,d2[0]
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vld1.32 {d4-d7}, [r3]!
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vmlal.u32 q11,d28,d2[1]
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vmlal.u32 q12,d28,d3[0]
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vzip.16 d29,d8
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vmlal.u32 q13,d28,d3[1]
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.LNEON_inner:
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vmlal.u32 q6,d29,d4[0]
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vld1.32 {d0-d3}, [r1]!
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vmlal.u32 q7,d29,d4[1]
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subs r8,r8,#8
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vmlal.u32 q8,d29,d5[0]
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vmlal.u32 q9,d29,d5[1]
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vst1.64 {q6-q7}, [r7,:256]!
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vmlal.u32 q10,d29,d6[0]
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vld1.64 {q6}, [r6, :128]!
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vmlal.u32 q11,d29,d6[1]
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vst1.64 {q8-q9}, [r7,:256]!
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vmlal.u32 q12,d29,d7[0]
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vld1.64 {q7-q8}, [r6, :256]!
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vmlal.u32 q13,d29,d7[1]
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vst1.64 {q10-q11}, [r7,:256]!
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vmlal.u32 q6,d28,d0[0]
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vld1.64 {q9-q10}, [r6, :256]!
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vmlal.u32 q7,d28,d0[1]
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vst1.64 {q12-q13}, [r7,:256]!
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vmlal.u32 q8,d28,d1[0]
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vld1.64 {q11-q12}, [r6, :256]!
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vmlal.u32 q9,d28,d1[1]
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vld1.32 {d4-d7}, [r3]!
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vmlal.u32 q10,d28,d2[0]
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vld1.64 {q13}, [r6, :128]!
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vmlal.u32 q11,d28,d2[1]
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vmlal.u32 q12,d28,d3[0]
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vmlal.u32 q13,d28,d3[1]
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bne .LNEON_inner
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vmlal.u32 q6,d29,d4[0]
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add r6,sp,#16
|
||
vmlal.u32 q7,d29,d4[1]
|
||
sub r1,r1,r5,lsl#2 @ rewind r1
|
||
vmlal.u32 q8,d29,d5[0]
|
||
vld1.64 {q5}, [sp,:128]
|
||
vmlal.u32 q9,d29,d5[1]
|
||
subs r9,r9,#1
|
||
|
||
vmlal.u32 q10,d29,d6[0]
|
||
vst1.64 {q6-q7}, [r7,:256]!
|
||
vmlal.u32 q11,d29,d6[1]
|
||
vld1.64 {q6}, [r6, :128]!
|
||
vshr.u64 d10,d10,#16
|
||
vst1.64 {q8-q9}, [r7,:256]!
|
||
vmlal.u32 q12,d29,d7[0]
|
||
vld1.64 {q7-q8}, [r6, :256]!
|
||
vmlal.u32 q13,d29,d7[1]
|
||
|
||
vst1.64 {q10-q11}, [r7,:256]!
|
||
vadd.u64 d10,d10,d11
|
||
vst1.64 {q12-q13}, [r7,:256]!
|
||
vshr.u64 d10,d10,#16
|
||
|
||
bne .LNEON_outer
|
||
|
||
mov r7,sp
|
||
mov r8,r5
|
||
|
||
.LNEON_tail:
|
||
vadd.u64 d12,d12,d10
|
||
vld1.64 {q9-q10}, [r6, :256]!
|
||
vshr.u64 d10,d12,#16
|
||
vadd.u64 d13,d13,d10
|
||
vld1.64 {q11-q12}, [r6, :256]!
|
||
vshr.u64 d10,d13,#16
|
||
vld1.64 {q13}, [r6, :128]!
|
||
vzip.16 d12,d13
|
||
|
||
.LNEON_tail2:
|
||
vadd.u64 d14,d14,d10
|
||
vst1.32 {d12[0]}, [r7, :32]!
|
||
vshr.u64 d10,d14,#16
|
||
vadd.u64 d15,d15,d10
|
||
vshr.u64 d10,d15,#16
|
||
vzip.16 d14,d15
|
||
|
||
vadd.u64 d16,d16,d10
|
||
vst1.32 {d14[0]}, [r7, :32]!
|
||
vshr.u64 d10,d16,#16
|
||
vadd.u64 d17,d17,d10
|
||
vshr.u64 d10,d17,#16
|
||
vzip.16 d16,d17
|
||
|
||
vadd.u64 d18,d18,d10
|
||
vst1.32 {d16[0]}, [r7, :32]!
|
||
vshr.u64 d10,d18,#16
|
||
vadd.u64 d19,d19,d10
|
||
vshr.u64 d10,d19,#16
|
||
vzip.16 d18,d19
|
||
|
||
vadd.u64 d20,d20,d10
|
||
vst1.32 {d18[0]}, [r7, :32]!
|
||
vshr.u64 d10,d20,#16
|
||
vadd.u64 d21,d21,d10
|
||
vshr.u64 d10,d21,#16
|
||
vzip.16 d20,d21
|
||
|
||
vadd.u64 d22,d22,d10
|
||
vst1.32 {d20[0]}, [r7, :32]!
|
||
vshr.u64 d10,d22,#16
|
||
vadd.u64 d23,d23,d10
|
||
vshr.u64 d10,d23,#16
|
||
vzip.16 d22,d23
|
||
|
||
vadd.u64 d24,d24,d10
|
||
vst1.32 {d22[0]}, [r7, :32]!
|
||
vshr.u64 d10,d24,#16
|
||
vadd.u64 d25,d25,d10
|
||
vld1.64 {q6}, [r6, :128]!
|
||
vshr.u64 d10,d25,#16
|
||
vzip.16 d24,d25
|
||
|
||
vadd.u64 d26,d26,d10
|
||
vst1.32 {d24[0]}, [r7, :32]!
|
||
vshr.u64 d10,d26,#16
|
||
vadd.u64 d27,d27,d10
|
||
vld1.64 {q7-q8}, [r6, :256]!
|
||
vshr.u64 d10,d27,#16
|
||
vzip.16 d26,d27
|
||
subs r8,r8,#8
|
||
vst1.32 {d26[0]}, [r7, :32]!
|
||
|
||
bne .LNEON_tail
|
||
|
||
vst1.32 {d10[0]}, [r7, :32] @ top-most bit
|
||
sub r3,r3,r5,lsl#2 @ rewind r3
|
||
subs r1,sp,#0 @ clear carry flag
|
||
add r2,sp,r5,lsl#2
|
||
|
||
.LNEON_sub:
|
||
ldmia r1!, {r4-r7}
|
||
ldmia r3!, {r8-r11}
|
||
sbcs r8, r4,r8
|
||
sbcs r9, r5,r9
|
||
sbcs r10,r6,r10
|
||
sbcs r11,r7,r11
|
||
teq r1,r2 @ preserves carry
|
||
stmia r0!, {r8-r11}
|
||
bne .LNEON_sub
|
||
|
||
ldr r10, [r1] @ load top-most bit
|
||
veor q0,q0,q0
|
||
sub r11,r2,sp @ this is num*4
|
||
veor q1,q1,q1
|
||
mov r1,sp
|
||
sub r0,r0,r11 @ rewind r0
|
||
mov r3,r2 @ second 3/4th of frame
|
||
sbcs r10,r10,#0 @ result is carry flag
|
||
|
||
.LNEON_copy_n_zap:
|
||
ldmia r1!, {r4-r7}
|
||
ldmia r0, {r8-r11}
|
||
movcc r8, r4
|
||
vst1.64 {q0-q1}, [r3,:256]! @ wipe
|
||
movcc r9, r5
|
||
movcc r10,r6
|
||
vst1.64 {q0-q1}, [r3,:256]! @ wipe
|
||
movcc r11,r7
|
||
ldmia r1, {r4-r7}
|
||
stmia r0!, {r8-r11}
|
||
sub r1,r1,#16
|
||
ldmia r0, {r8-r11}
|
||
movcc r8, r4
|
||
vst1.64 {q0-q1}, [r1,:256]! @ wipe
|
||
movcc r9, r5
|
||
movcc r10,r6
|
||
vst1.64 {q0-q1}, [r3,:256]! @ wipe
|
||
movcc r11,r7
|
||
teq r1,r2 @ preserves carry
|
||
stmia r0!, {r8-r11}
|
||
bne .LNEON_copy_n_zap
|
||
|
||
sub sp,ip,#96
|
||
vldmia sp!,{d8-d15}
|
||
ldmia sp!,{r4-r11}
|
||
bx lr @ .word 0xe12fff1e
|
||
.size bn_mul8x_mont_neon,.-bn_mul8x_mont_neon
|
||
#endif
|
||
.asciz "Montgomery multiplication for ARMv4/NEON, CRYPTOGAMS by <appro@openssl.org>"
|
||
.align 2
|
||
#if __ARM_MAX_ARCH__>=7
|
||
.comm OPENSSL_armcap_P,4,4
|
||
#endif
|