824b48eff3
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation. On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores. On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented. Reviewed by: mizhka Approved by: adrian (mentor, implicit)
68 lines
2.4 KiB
C
68 lines
2.4 KiB
C
/*-
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* Copyright (c) 2015 Landon Fuller <landon@landonf.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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#ifndef _BHND_BHNDB_PCIVAR_H_
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#define _BHND_BHNDB_PCIVAR_H_
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#include "bhndbvar.h"
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/*
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* bhndb(4) PCI driver subclass.
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*/
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DECLARE_CLASS(bhndb_pci_driver);
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struct bhndb_pci_softc;
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/*
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* An interconnect-specific function implementing BHNDB_SET_WINDOW_ADDR
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*/
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typedef int (*bhndb_pci_set_regwin_t)(struct bhndb_pci_softc *sc,
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const struct bhndb_regwin *rw, bhnd_addr_t addr);
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/* bhndb_pci interrupt state */
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struct bhndb_pci_intr {
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int msi_count; /**< MSI count, or 0 */
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int intr_rid; /**< interrupt resource ID.*/
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};
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struct bhndb_pci_softc {
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struct bhndb_softc bhndb; /**< parent softc */
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device_t dev; /**< bridge device */
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device_t parent; /**< parent PCI device */
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bhnd_devclass_t pci_devclass; /**< PCI core's devclass */
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struct bhndb_pci_intr intr; /**< PCI interrupt config */
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bhndb_pci_set_regwin_t set_regwin; /**< regwin handler */
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};
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#endif /* _BHND_BHNDB_PCIVAR_H_ */
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