317 lines
9.6 KiB
C
317 lines
9.6 KiB
C
/*-
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* Copyright (c) 2011, 2016 Chelsio Communications, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __T4_REGS_VALUES_H__
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#define __T4_REGS_VALUES_H__
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/*
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* This file contains definitions for various T4 register value hardware
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* constants. The types of values encoded here are predominantly those for
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* register fields which control "modal" behavior. For the most part, we do
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* not include definitions for register fields which are simple numeric
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* metrics, etc.
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*
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* These new "modal values" use a naming convention which matches the
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* currently existing macros in t4_reg.h. For register field FOO which would
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* have S_FOO, M_FOO, V_FOO() and G_FOO() macros, we introduce X_FOO_{MODE}
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* definitions. These can be used as V_FOO(X_FOO_MODE) or as (G_FOO(x) ==
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* X_FOO_MODE).
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*
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* Note that this should all be part of t4_regs.h but the toolset used to
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* generate that file doesn't [yet] have the capability of collecting these
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* constants.
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*/
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/*
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* SGE definitions.
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* ================
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*/
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/*
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* SGE register field values.
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*/
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/* CONTROL register */
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#define X_FLSPLITMODE_FLSPLITMIN 0
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#define X_FLSPLITMODE_ETHHDR 1
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#define X_FLSPLITMODE_IPHDR 2
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#define X_FLSPLITMODE_TCPHDR 3
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#define X_DCASYSTYPE_FSB 0
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#define X_DCASYSTYPE_CSI 1
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#define X_EGSTATPAGESIZE_64B 0
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#define X_EGSTATPAGESIZE_128B 1
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#define X_RXPKTCPLMODE_DATA 0
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#define X_RXPKTCPLMODE_SPLIT 1
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#define X_INGPCIEBOUNDARY_SHIFT 5
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#define X_INGPCIEBOUNDARY_32B 0
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#define X_INGPCIEBOUNDARY_64B 1
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#define X_INGPCIEBOUNDARY_128B 2
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#define X_INGPCIEBOUNDARY_256B 3
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#define X_INGPCIEBOUNDARY_512B 4
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#define X_INGPCIEBOUNDARY_1024B 5
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#define X_INGPCIEBOUNDARY_2048B 6
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#define X_INGPCIEBOUNDARY_4096B 7
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#define X_T6_INGPADBOUNDARY_SHIFT 3
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#define X_T6_INGPADBOUNDARY_8B 0
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#define X_T6_INGPADBOUNDARY_16B 1
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#define X_T6_INGPADBOUNDARY_32B 2
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#define X_T6_INGPADBOUNDARY_64B 3
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#define X_T6_INGPADBOUNDARY_128B 4
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#define X_T6_INGPADBOUNDARY_256B 5
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#define X_T6_INGPADBOUNDARY_512B 6
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#define X_T6_INGPADBOUNDARY_1024B 7
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#define X_INGPADBOUNDARY_SHIFT 5
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#define X_INGPADBOUNDARY_32B 0
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#define X_INGPADBOUNDARY_64B 1
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#define X_INGPADBOUNDARY_128B 2
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#define X_INGPADBOUNDARY_256B 3
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#define X_INGPADBOUNDARY_512B 4
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#define X_INGPADBOUNDARY_1024B 5
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#define X_INGPADBOUNDARY_2048B 6
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#define X_INGPADBOUNDARY_4096B 7
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#define X_EGRPCIEBOUNDARY_SHIFT 5
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#define X_EGRPCIEBOUNDARY_32B 0
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#define X_EGRPCIEBOUNDARY_64B 1
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#define X_EGRPCIEBOUNDARY_128B 2
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#define X_EGRPCIEBOUNDARY_256B 3
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#define X_EGRPCIEBOUNDARY_512B 4
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#define X_EGRPCIEBOUNDARY_1024B 5
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#define X_EGRPCIEBOUNDARY_2048B 6
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#define X_EGRPCIEBOUNDARY_4096B 7
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/* CONTROL2 register */
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#define X_INGPACKBOUNDARY_SHIFT 5 // *most* of the values ...
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#define X_INGPACKBOUNDARY_16B 0 // Note weird value!
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#define X_INGPACKBOUNDARY_64B 1
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#define X_INGPACKBOUNDARY_128B 2
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#define X_INGPACKBOUNDARY_256B 3
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#define X_INGPACKBOUNDARY_512B 4
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#define X_INGPACKBOUNDARY_1024B 5
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#define X_INGPACKBOUNDARY_2048B 6
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#define X_INGPACKBOUNDARY_4096B 7
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/* GTS register */
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#define SGE_TIMERREGS 6
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#define X_TIMERREG_COUNTER0 0
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#define X_TIMERREG_COUNTER1 1
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#define X_TIMERREG_COUNTER2 2
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#define X_TIMERREG_COUNTER3 3
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#define X_TIMERREG_COUNTER4 4
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#define X_TIMERREG_COUNTER5 5
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#define X_TIMERREG_RESTART_COUNTER 6
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#define X_TIMERREG_UPDATE_CIDX 7
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/*
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* Egress Context field values
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*/
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#define EC_WR_UNITS 16
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#define X_FETCHBURSTMIN_SHIFT 4
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#define X_FETCHBURSTMIN_16B 0
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#define X_FETCHBURSTMIN_32B 1
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#define X_FETCHBURSTMIN_64B 2
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#define X_FETCHBURSTMIN_128B 3
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#define X_FETCHBURSTMAX_SHIFT 6
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#define X_FETCHBURSTMAX_64B 0
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#define X_FETCHBURSTMAX_128B 1
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#define X_FETCHBURSTMAX_256B 2
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#define X_FETCHBURSTMAX_512B 3
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#define X_HOSTFCMODE_NONE 0
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#define X_HOSTFCMODE_INGRESS_QUEUE 1
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#define X_HOSTFCMODE_STATUS_PAGE 2
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#define X_HOSTFCMODE_BOTH 3
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#define X_HOSTFCOWNER_UP 0
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#define X_HOSTFCOWNER_SGE 1
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#define X_CIDXFLUSHTHRESH_1 0
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#define X_CIDXFLUSHTHRESH_2 1
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#define X_CIDXFLUSHTHRESH_4 2
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#define X_CIDXFLUSHTHRESH_8 3
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#define X_CIDXFLUSHTHRESH_16 4
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#define X_CIDXFLUSHTHRESH_32 5
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#define X_CIDXFLUSHTHRESH_64 6
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#define X_CIDXFLUSHTHRESH_128 7
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#define X_IDXSIZE_UNIT 64
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#define X_BASEADDRESS_ALIGN 512
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/*
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* Ingress Context field values
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*/
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#define X_UPDATESCHEDULING_TIMER 0
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#define X_UPDATESCHEDULING_COUNTER_OPTTIMER 1
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#define X_UPDATEDELIVERY_NONE 0
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#define X_UPDATEDELIVERY_INTERRUPT 1
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#define X_UPDATEDELIVERY_STATUS_PAGE 2
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#define X_UPDATEDELIVERY_BOTH 3
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#define X_INTERRUPTDESTINATION_PCIE 0
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#define X_INTERRUPTDESTINATION_IQ 1
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#define X_QUEUEENTRYSIZE_16B 0
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#define X_QUEUEENTRYSIZE_32B 1
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#define X_QUEUEENTRYSIZE_64B 2
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#define X_QUEUEENTRYSIZE_128B 3
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#define IC_SIZE_UNIT 16
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#define IC_BASEADDRESS_ALIGN 512
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#define X_RSPD_TYPE_FLBUF 0
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#define X_RSPD_TYPE_CPL 1
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#define X_RSPD_TYPE_INTR 2
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/*
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* Context field definitions. This is by no means a complete list of SGE
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* Context fields. In the vast majority of cases the firmware initializes
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* things the way they need to be set up. But in a few small cases, we need
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* to compute new values and ship them off to the firmware to be applied to
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* the SGE Conexts ...
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*/
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/*
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* Congestion Manager Definitions.
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*/
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#define S_CONMCTXT_CNGTPMODE 19
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#define M_CONMCTXT_CNGTPMODE 0x3
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#define V_CONMCTXT_CNGTPMODE(x) ((x) << S_CONMCTXT_CNGTPMODE)
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#define G_CONMCTXT_CNGTPMODE(x) \
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(((x) >> S_CONMCTXT_CNGTPMODE) & M_CONMCTXT_CNGTPMODE)
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#define S_CONMCTXT_CNGCHMAP 0
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#define M_CONMCTXT_CNGCHMAP 0xffff
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#define V_CONMCTXT_CNGCHMAP(x) ((x) << S_CONMCTXT_CNGCHMAP)
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#define G_CONMCTXT_CNGCHMAP(x) \
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(((x) >> S_CONMCTXT_CNGCHMAP) & M_CONMCTXT_CNGCHMAP)
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#define X_CONMCTXT_CNGTPMODE_DISABLE 0
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#define X_CONMCTXT_CNGTPMODE_QUEUE 1
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#define X_CONMCTXT_CNGTPMODE_CHANNEL 2
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#define X_CONMCTXT_CNGTPMODE_BOTH 3
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/*
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* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
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* The User Doorbells are each 128 bytes in length with a Simple Doorbell at
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* offsets 8x and a Write Combining single 64-byte Egress Queue Unit
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* (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64. For Ingress Queues,
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* we have a Going To Sleep register at offsets 8x+4.
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*
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* As noted above, we have many instances of the Simple Doorbell and Going To
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* Sleep registers at offsets 8x and 8x+4, respectively. We want to use a
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* non-64-byte aligned offset for the Simple Doorbell in order to attempt to
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* avoid buffering of the writes to the Simple Doorbell and we want to use a
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* non-contiguous offset for the Going To Sleep writes in order to avoid
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* possible combining between them.
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*/
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#define SGE_UDB_SIZE 128
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#define SGE_UDB_KDOORBELL 8
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#define SGE_UDB_GTS 20
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#define SGE_UDB_WCDOORBELL 64
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/*
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* CIM definitions.
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* ================
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*/
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/*
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* CIM register field values.
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*/
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#define X_MBOWNER_NONE 0
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#define X_MBOWNER_FW 1
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#define X_MBOWNER_PL 2
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#define X_MBOWNER_FW_DEFERRED 3
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/*
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* PCI-E definitions.
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* ==================
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*/
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#define X_WINDOW_SHIFT 10
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#define X_PCIEOFST_SHIFT 10
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/*
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* TP definitions.
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* ===============
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*/
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/*
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* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
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* Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
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* selects for a particular field being present. These fields, when present
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* in the Compressed Filter Tuple, have the following widths in bits.
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*/
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#define S_FT_FIRST S_FCOE
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#define S_FT_LAST S_FRAGMENTATION
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#define W_FT_FCOE 1
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#define W_FT_PORT 3
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#define W_FT_VNIC_ID 17
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#define W_FT_VLAN 17
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#define W_FT_TOS 8
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#define W_FT_PROTOCOL 8
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#define W_FT_ETHERTYPE 16
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#define W_FT_MACMATCH 9
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#define W_FT_MPSHITTYPE 3
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#define W_FT_FRAGMENTATION 1
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/*
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* Some of the Compressed Filter Tuple fields have internal structure. These
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* bit shifts/masks describe those structures. All shifts are relative to the
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* base position of the fields within the Compressed Filter Tuple
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*/
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#define S_FT_VLAN_VLD 16
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#define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD)
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#define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U)
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#define S_FT_VNID_ID_VF 0
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#define M_FT_VNID_ID_VF 0x7fU
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#define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF)
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#define G_FT_VNID_ID_VF(x) (((x) >> S_FT_VNID_ID_VF) & M_FT_VNID_ID_VF)
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#define S_FT_VNID_ID_PF 7
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#define M_FT_VNID_ID_PF 0x7U
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#define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF)
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#define G_FT_VNID_ID_PF(x) (((x) >> S_FT_VNID_ID_PF) & M_FT_VNID_ID_PF)
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#define S_FT_VNID_ID_VLD 16
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#define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD)
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#define F_FT_VNID_ID_VLD(x) V_FT_VNID_ID_VLD(1U)
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#endif /* __T4_REGS_VALUES_H__ */
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