cc9fce5ad7
HD64570 chip. Both the 2 and 4 port cards is supported and auto detected. Line speeds of up to 2Mbps is possible. At this speed about 85% of the bandwidth is usable with 486DX processors. The standard FreeBSD sppp code is used for the link level layer. The default protocol used is PPP. The Cisco HDLC protocol can be used by adding "link2" to the ifconfig line in /etc/sysconfig or where ever ifconfig is run. At the moment only the V.35 and X.21 interfaces is supported. The others may need tweaks to the clock selection code. Submitted by: John Hay <jhay@mikom.csir.co.za>
142 lines
4.7 KiB
C
142 lines
4.7 KiB
C
/*
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* Copyright (c) 1995 John Hay. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by [your name]
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* and [any other names deserving credit ]
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY [your name] AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_arregs.h,v 1.6 1995/11/14 19:50:57 jhay Exp $
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*/
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#ifndef _IF_ARREGS_H_
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#define _IF_ARREGS_H_
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#define NCHAN 2 /* A HD64570 chip have 2 channels */
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#define NPORT 4 /* A ArNet board can have 4 ports or */
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/* channels */
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#define AR_BUF_SIZ 512
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#define ARC_IO_SIZ 0x10
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#define ARC_WIN_SIZ 0x00004000
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#define ARC_WIN_MSK (ARC_WIN_SIZ - 1)
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#define ARC_WIN_SHFT 14
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#define AR_ID_5 0x00 /* RO, Card probe '5' */
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#define AR_ID_7 0x01 /* RO, Card probe '7' */
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#define AR_ID_0 0x02 /* RO, Card probe '0' */
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#define AR_BMI 0x03 /* RO, Bus, mem and interface type */
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#define AR_REV 0x04 /* RO, Adapter revision */
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#define AR_PNUM 0x05 /* RO, Port number */
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#define AR_HNDSH 0x06 /* RO, Supported handshake */
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#define AR_ISTAT 0x07 /* RO, DCD and Interrupt status */
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#define AR_MSCA_EN 0x08 /* WO, Memory and SCA enable */
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#define AR_TXC_DTR0 0x09 /* WO, Tx Clock and DTR control 0 + 1 */
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#define AR_SEC_PAL 0x0A /* RW, Security PAL */
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#define AR_INT_ACK0 0x0B /* RO, Interrupt Acknowledge 0 + 1 */
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#define AR_INT_SEL 0x0C /* RW, Interrupt Select */
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#define AR_MEM_SEL 0x0D /* RW, Memory Select */
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#define AR_INT_ACK2 0x0E /* RO, Interrupt Acknowledge 2 + 3 */
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#define AR_TXC_DTR2 0x0E /* WO, Tx Clock and DTR control 2 + 3 */
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/* Bus memory and interface type */
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#define AR_BUS_MSK 0x03
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#define AR_BUS_ISA 0x00
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#define AR_BUS_MCA 0x01
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#define AR_BUS_EISA 0x02
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#define AR_MEM_MSK 0x1C
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#define AR_MEM_SHFT 0x02
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#define AR_MEM_64K 0x00
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#define AR_MEM_128K 0x04
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#define AR_MEM_256K 0x08
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#define AR_MEM_512K 0x0C
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/*
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* EIA-232
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* V.35/EIA-232
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* EIA-530
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* X.21
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* EIA-530/X.21 Combo
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*/
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#define AR_IFACE_MSK 0xE0
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#define AR_IFACE_SHFT 0x05
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#define AR_IFACE_EIA_232 0x00 /* Only on the 570 card, not 570i */
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#define AR_IFACE_V_35 0x20 /* Selectable between V.35 and EIA-232 */
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#define AR_IFACE_EIA_530 0x40
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#define AR_IFACE_X_21 0x60
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#define AR_IFACE_COMBO 0xC0 /* X.21 / EIA-530 */
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/* Supported Handshake signals */
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#define AR_SHSK_DTR 0x01
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#define AR_SHSK_RTS 0x02
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#define AR_SHSK_CTS 0x10
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#define AR_SHSK_DSR 0x20
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#define AR_SHSK_RI 0x40
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#define AR_SHSK_DCD 0x80
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/* DCD and Interrupt status */
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#define AR_BD_INT 0x01
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#define AR_INT_0 0x20
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#define AR_INT_1 0x40
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#define AR_DCD_MSK 0x1E
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#define AR_DCD_SHFT 0x01
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#define AR_DCD_0 0x02
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#define AR_DCD_1 0x04
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#define AR_DCD_2 0x08
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#define AR_DCD_3 0x10
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/* Memory and SCA enable */
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#define AR_WIN_MSK 0x1F
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#define AR_SEL_SCA_0 0x00
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#define AR_SEL_SCA_1 0x20
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#define AR_ENA_SCA 0x40
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#define AR_ENA_MEM 0x80
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/* Transmit Clock and DTR and RESET */
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#define AR_TXC_DTR_TX0 0x01
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#define AR_TXC_DTR_TX1 0x02
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#define AR_TXC_DTR_DTR0 0x04
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#define AR_TXC_DTR_DTR1 0x08
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#define AR_TXC_DTR_TXCS0 0x10
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#define AR_TXC_DTR_TXCS1 0x20
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#define AR_TXC_DTR_NOTRESET 0x40
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#define AR_TXC_DTR_RESET 0x00
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/* Interrupt select register */
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#define AR_INTS_CEN 0x01
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#define AR_INTS_ISEL0 0x02
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#define AR_INTS_ISEL1 0x04
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#define AR_INTS_ISEL2 0x08
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#define AR_INTS_CMA14 0x10
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#define AR_INTS_CMA15 0x20
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/* Memory select register */
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#endif /* _IF_ARREGS_H_ */
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