271 lines
7.9 KiB
C
271 lines
7.9 KiB
C
/*-
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* Copyright (c) 2001 Jake Burkholder.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CPUFUNC_H_
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#define _MACHINE_CPUFUNC_H_
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#include <machine/asi.h>
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#include <machine/pstate.h>
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struct thread;
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/*
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* Membar operand macros for use in other macros when # is a special
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* character. Keep these in sync with what the hardware expects.
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*/
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#define C_Lookaside (0)
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#define C_MemIssue (1)
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#define C_Sync (2)
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#define M_LoadLoad (0)
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#define M_StoreLoad (1)
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#define M_LoadStore (2)
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#define M_StoreStore (3)
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#define CMASK_SHIFT (4)
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#define MMASK_SHIFT (0)
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#define CMASK_GEN(bit) ((1 << (bit)) << CMASK_SHIFT)
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#define MMASK_GEN(bit) ((1 << (bit)) << MMASK_SHIFT)
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#define Lookaside CMASK_GEN(C_Lookaside)
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#define MemIssue CMASK_GEN(C_MemIssue)
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#define Sync CMASK_GEN(C_Sync)
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#define LoadLoad MMASK_GEN(M_LoadLoad)
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#define StoreLoad MMASK_GEN(M_StoreLoad)
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#define LoadStore MMASK_GEN(M_LoadStore)
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#define StoreStore MMASK_GEN(M_StoreStore)
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#define casa(rs1, rs2, rd, asi) ({ \
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u_int __rd = (uint32_t)(rd); \
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__asm __volatile("casa [%2] %3, %4, %0" \
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: "+r" (__rd), "=m" (*rs1) \
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: "r" (rs1), "n" (asi), "r" (rs2), "m" (*rs1)); \
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__rd; \
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})
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#define casxa(rs1, rs2, rd, asi) ({ \
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u_long __rd = (uint64_t)(rd); \
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__asm __volatile("casxa [%2] %3, %4, %0" \
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: "+r" (__rd), "=m" (*rs1) \
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: "r" (rs1), "n" (asi), "r" (rs2), "m" (*rs1)); \
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__rd; \
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})
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#define flush(va) do { \
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__asm __volatile("flush %0" : : "r" (va)); \
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} while (0)
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#define flushw() do { \
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__asm __volatile("flushw" : :); \
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} while (0)
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#define mov(val, reg) do { \
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__asm __volatile("mov %0, %" __XSTRING(reg) : : "r" (val)); \
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} while (0)
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/* Generate ld*a/st*a functions for non-constant ASIs. */
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#define LDNC_GEN(tp, o) \
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static __inline tp \
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o ## _nc(caddr_t va, int asi) \
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{ \
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tp r; \
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__asm __volatile("wr %2, 0, %%asi;" #o " [%1] %%asi, %0"\
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: "=r" (r) : "r" (va), "r" (asi)); \
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return (r); \
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}
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LDNC_GEN(u_char, lduba);
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LDNC_GEN(u_short, lduha);
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LDNC_GEN(u_int, lduwa);
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LDNC_GEN(u_long, ldxa);
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#define LD_GENERIC(va, asi, op, type) ({ \
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type __r; \
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__asm __volatile(#op " [%1] %2, %0" \
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: "=r" (__r) : "r" (va), "n" (asi)); \
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__r; \
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})
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#define lduba(va, asi) LD_GENERIC(va, asi, lduba, u_char)
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#define lduha(va, asi) LD_GENERIC(va, asi, lduha, u_short)
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#define lduwa(va, asi) LD_GENERIC(va, asi, lduwa, u_int)
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#define ldxa(va, asi) LD_GENERIC(va, asi, ldxa, u_long)
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#define STNC_GEN(tp, o) \
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static __inline void \
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o ## _nc(caddr_t va, int asi, tp val) \
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{ \
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__asm __volatile("wr %2, 0, %%asi;" #o " %0, [%1] %%asi"\
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: : "r" (val), "r" (va), "r" (asi)); \
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}
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STNC_GEN(u_char, stba);
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STNC_GEN(u_short, stha);
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STNC_GEN(u_int, stwa);
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STNC_GEN(u_long, stxa);
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#define ST_GENERIC(va, asi, val, op) \
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__asm __volatile(#op " %0, [%1] %2" \
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: : "r" (val), "r" (va), "n" (asi)); \
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#define stba(va, asi, val) ST_GENERIC(va, asi, val, stba)
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#define stha(va, asi, val) ST_GENERIC(va, asi, val, stha)
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#define stwa(va, asi, val) ST_GENERIC(va, asi, val, stwa)
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#define stxa(va, asi, val) ST_GENERIC(va, asi, val, stxa)
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/*
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* Attempt to read from addr, val. If a Data Access Error trap happens,
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* they return -1 and the contents of val is undefined. A return of 0
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* means no trap happened, and the contents of val is valid.
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*/
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int fasword8(u_long asi, void *addr, uint8_t *val);
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int fasword16(u_long asi, void *addr, uint16_t *val);
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int fasword32(u_long asi, void *addr, uint32_t *val);
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#define membar(mask) do { \
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__asm __volatile("membar %0" : : "n" (mask) : "memory"); \
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} while (0)
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#define rd(name) ({ \
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uint64_t __sr; \
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__asm __volatile("rd %%" #name ", %0" : "=r" (__sr) :); \
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__sr; \
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})
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#define wr(name, val, xorval) do { \
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__asm __volatile("wr %0, %1, %%" #name \
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: : "r" (val), "rI" (xorval)); \
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} while (0)
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#define rdpr(name) ({ \
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uint64_t __pr; \
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__asm __volatile("rdpr %%" #name", %0" : "=r" (__pr) :); \
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__pr; \
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})
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#define wrpr(name, val, xorval) do { \
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__asm __volatile("wrpr %0, %1, %%" #name \
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: : "r" (val), "rI" (xorval)); \
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} while (0)
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/*
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* Trick GAS/GCC into compiling access to TICK/(S)TICK_COMPARE independently
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* of the selected instruction set.
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*/
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#define rdtickcmpr() rd(asr23)
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#define rdstick() rd(asr24)
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#define rdstickcmpr() rd(asr25)
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#define wrtickcmpr(val, xorval) wr(asr23, (val), (xorval))
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#define wrstick(val, xorval) wr(asr24, (val), (xorval))
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#define wrstickcmpr(val, xorval) wr(asr25, (val), (xorval))
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/*
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* Macro intended to be used instead of wr(asr23, val, xorval) for writing to
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* the TICK_COMPARE register in order to avoid a bug in BlackBird CPUs that
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* can cause these writes to fail under certain conditions which in turn
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* causes the hardclock to stop. The workaround is to read the TICK_COMPARE
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* register back immediately after writing to it with these two instructions
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* aligned to a quadword boundary in order to ensure that I$ misses won't
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* split them up.
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*/
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#define wrtickcmpr_bbwar(val, xorval) ({ \
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__asm __volatile( \
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" ba,pt %%xcc, 1f ; " \
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" nop ; " \
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" .align 128 ; " \
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"1: wr %0, %1, %%asr23 ; " \
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" rd %%asr23, %%g0 ; " \
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: : "r" (val), "rI" (xorval)); \
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})
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static __inline void
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breakpoint(void)
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{
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__asm __volatile("ta %%xcc, 1" : :);
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}
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static __inline register_t
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intr_disable(void)
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{
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register_t s;
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s = rdpr(pstate);
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wrpr(pstate, s & ~PSTATE_IE, 0);
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return (s);
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}
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#define intr_restore(s) wrpr(pstate, (s), 0)
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/*
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* In some places, it is required that the store is directly followed by a
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* membar #Sync. Don't trust the compiler to not insert instructions in
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* between. We also need to disable interrupts completely.
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*/
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#define stxa_sync(va, asi, val) do { \
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register_t s; \
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s = intr_disable(); \
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__asm __volatile("stxa %0, [%1] %2; membar #Sync" \
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: : "r" (val), "r" (va), "n" (asi)); \
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intr_restore(s); \
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} while (0)
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void ascopy(u_long asi, vm_offset_t src, vm_offset_t dst, size_t len);
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void ascopyfrom(u_long sasi, vm_offset_t src, caddr_t dst, size_t len);
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void ascopyto(caddr_t src, u_long dasi, vm_offset_t dst, size_t len);
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void aszero(u_long asi, vm_offset_t dst, size_t len);
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/*
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* Ultrasparc II doesn't implement popc in hardware.
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*/
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#if 0
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#define HAVE_INLINE_FFS
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/*
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* See page 202 of the SPARC v9 Architecture Manual.
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*/
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static __inline int
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ffs(int mask)
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{
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int result;
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int neg;
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int tmp;
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__asm __volatile(
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" neg %3, %1 ; "
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" xnor %3, %1, %2 ; "
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" popc %2, %0 ; "
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" movrz %3, %%g0, %0 ; "
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: "=r" (result), "=r" (neg), "=r" (tmp) : "r" (mask));
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return (result);
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}
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#endif
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#undef LDNC_GEN
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#undef STNC_GEN
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#endif /* !_MACHINE_CPUFUNC_H_ */
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