156 lines
4.8 KiB
C
156 lines
4.8 KiB
C
/*-
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* Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_RISCVREG_H_
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#define _MACHINE_RISCVREG_H_
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/* Machine mode requests */
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#define ECALL_MTIMECMP 0x1
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#define ECALL_CLEAR_PENDING 0x2
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#define ECALL_HTIF_CMD 0x3
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#define ECALL_HTIF_GET_ENTRY 0x4
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#define ECALL_MCPUID_GET 0x5
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#define ECALL_MIMPID_GET 0x6
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#define EXCP_SHIFT 0
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#define EXCP_MASK (0xf << EXCP_SHIFT)
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#define EXCP_INSTR_ADDR_MISALIGNED 0
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#define EXCP_INSTR_ACCESS_FAULT 1
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#define EXCP_INSTR_ILLEGAL 2
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#define EXCP_INSTR_BREAKPOINT 3
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#define EXCP_LOAD_ADDR_MISALIGNED 4
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#define EXCP_LOAD_ACCESS_FAULT 5
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#define EXCP_STORE_ADDR_MISALIGNED 6
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#define EXCP_STORE_ACCESS_FAULT 7
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#define EXCP_UMODE_ENV_CALL 8
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#define EXCP_SMODE_ENV_CALL 9
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#define EXCP_HMODE_ENV_CALL 10
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#define EXCP_MMODE_ENV_CALL 11
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#define EXCP_INTR (1 << 31)
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#define EXCP_INTR_SOFTWARE 0
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#define EXCP_INTR_TIMER 1
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#define EXCP_INTR_HTIF 2
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#define SSTATUS_IE (1 << 0)
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#define SSTATUS_PIE (1 << 3)
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#define SSTATUS_PS (1 << 4)
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#define MSTATUS_MPRV (1 << 16)
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#define MSTATUS_PRV_SHIFT 1
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#define MSTATUS_PRV1_SHIFT 4
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#define MSTATUS_PRV2_SHIFT 7
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#define MSTATUS_PRV_MASK (0x3 << MSTATUS_PRV_SHIFT)
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#define MSTATUS_PRV_U 0 /* user */
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#define MSTATUS_PRV_S 1 /* supervisor */
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#define MSTATUS_PRV_H 2 /* hypervisor */
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#define MSTATUS_PRV_M 3 /* machine */
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#define MSTATUS_VM_SHIFT 17
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#define MSTATUS_VM_MASK 0x1f
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#define MSTATUS_VM_MBARE 0
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#define MSTATUS_VM_MBB 1
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#define MSTATUS_VM_MBBID 2
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#define MSTATUS_VM_SV32 8
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#define MSTATUS_VM_SV39 9
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#define MSTATUS_VM_SV48 10
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#define MIE_SSIE (1 << 1)
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#define MIE_HSIE (1 << 2)
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#define MIE_MSIE (1 << 3)
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#define MIE_STIE (1 << 5)
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#define MIE_HTIE (1 << 6)
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#define MIE_MTIE (1 << 7)
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#define MIP_SSIP (1 << 1)
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#define MIP_HSIP (1 << 2)
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#define MIP_MSIP (1 << 3)
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#define MIP_STIP (1 << 5)
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#define MIP_HTIP (1 << 6)
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#define MIP_MTIP (1 << 7)
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#define SR_IE (1 << 0)
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#define SR_IE1 (1 << 3)
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#define SR_IE2 (1 << 6)
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#define SR_IE3 (1 << 9)
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#define SIE_SSIE (1 << 1)
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#define SIE_STIE (1 << 5)
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/* Note: sip register is not yet implement in Spike simulator */
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#define SIP_STIP (1 << 5)
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#define CSR_ZIMM(val) \
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(__builtin_constant_p(val) && ((u_long)(val) < 32))
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#define csr_swap(csr, val) \
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({ if (CSR_ZIMM(val)) \
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__asm __volatile("csrrwi %0, " #csr ", %1" \
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: "=r" (val) : "i" (val)); \
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else \
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__asm __volatile("csrrw %0, " #csr ", %1" \
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: "=r" (val) : "r" (val)); \
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val; \
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})
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#define csr_write(csr, val) \
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({ if (CSR_ZIMM(val)) \
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__asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \
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else \
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__asm __volatile("csrw " #csr ", %0" :: "r" (val)); \
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})
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#define csr_set(csr, val) \
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({ if (CSR_ZIMM(val)) \
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__asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \
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else \
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__asm __volatile("csrs " #csr ", %0" :: "r" (val)); \
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})
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#define csr_clear(csr, val) \
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({ if (CSR_ZIMM(val)) \
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__asm __volatile("csrci " #csr ", %0" :: "i" (val)); \
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else \
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__asm __volatile("csrc " #csr ", %0" :: "r" (val)); \
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})
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#define csr_read(csr) \
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({ u_long val; \
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__asm __volatile("csrr %0, " #csr : "=r" (val)); \
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val; \
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})
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#endif /* !_MACHINE_RISCVREG_H_ */
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