4541f27356
the main processing queue, clear the NAK counter for any associated BULK or CONTROL transfers and poll the endpoint(s) for 1 millisecond at 125us rate interval, before going into slow, 10ms, NAK polling mode again. This has the effect that typical ping-ping protocols respond quicker when initiated from the USB host. MFC after: 2 weeks
215 lines
6.2 KiB
C
215 lines
6.2 KiB
C
/* $FreeBSD$ */
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/*-
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* Copyright (c) 2012 Hans Petter Selasky. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _DWC_OTG_H_
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#define _DWC_OTG_H_
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#define DWC_OTG_MAX_DEVICES MIN(USB_MAX_DEVICES, 32)
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#define DWC_OTG_FRAME_MASK 0x7FF
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#define DWC_OTG_MAX_TXP 4
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#define DWC_OTG_MAX_TXN (0x200 * DWC_OTG_MAX_TXP)
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#define DWC_OTG_MAX_CHANNELS 16
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#define DWC_OTG_MAX_ENDPOINTS 16
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#define DWC_OTG_HOST_TIMER_RATE 10 /* ms */
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#define DWC_OTG_TT_SLOT_MAX 8
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#define DWC_OTG_SLOT_IDLE_MAX 4
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#define DWC_OTG_SLOT_IDLE_MIN 2
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#define DWC_OTG_NAK_MAX 8 /* 1 ms */
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#define DWC_OTG_READ_4(sc, reg) \
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bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
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#define DWC_OTG_WRITE_4(sc, reg, data) \
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bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
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struct dwc_otg_td;
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struct dwc_otg_softc;
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typedef uint8_t (dwc_otg_cmd_t)(struct dwc_otg_td *td);
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struct dwc_otg_td {
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struct dwc_otg_td *obj_next;
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dwc_otg_cmd_t *func;
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struct usb_page_cache *pc;
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uint32_t tx_bytes;
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uint32_t offset;
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uint32_t remainder;
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uint32_t hcchar; /* HOST CFG */
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uint32_t hcsplt; /* HOST CFG */
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uint16_t max_packet_size; /* packet_size */
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uint16_t npkt;
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uint8_t max_packet_count; /* packet_count */
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uint8_t errcnt;
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uint8_t tmr_res;
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uint8_t tmr_val;
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uint8_t did_nak; /* NAK counter */
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uint8_t ep_no;
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uint8_t ep_type;
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uint8_t channel[2];
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uint8_t tt_start_slot; /* TT data */
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uint8_t tt_complete_slot; /* TT data */
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uint8_t tt_xactpos; /* TT data */
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uint8_t state;
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#define DWC_CHAN_ST_START 0
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#define DWC_CHAN_ST_WAIT_ANE 1
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#define DWC_CHAN_ST_WAIT_S_ANE 2
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#define DWC_CHAN_ST_WAIT_C_ANE 3
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#define DWC_CHAN_ST_WAIT_C_PKT 4
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#define DWC_CHAN_ST_TX_PKT_ISOC 5
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#define DWC_CHAN_ST_TX_WAIT_ISOC 6
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uint8_t error:1;
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uint8_t error_any:1;
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uint8_t error_stall:1;
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uint8_t alt_next:1;
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uint8_t short_pkt:1;
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uint8_t did_stall:1;
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uint8_t toggle:1;
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uint8_t set_toggle:1;
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uint8_t got_short:1;
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uint8_t tt_scheduled:1;
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uint8_t tt_channel_tog:1;
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};
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struct dwc_otg_std_temp {
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dwc_otg_cmd_t *func;
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struct usb_page_cache *pc;
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struct dwc_otg_td *td;
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struct dwc_otg_td *td_next;
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uint32_t len;
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uint32_t offset;
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uint16_t max_frame_size;
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uint8_t short_pkt;
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/*
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* short_pkt = 0: transfer should be short terminated
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* short_pkt = 1: transfer should not be short terminated
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*/
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uint8_t setup_alt_next;
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uint8_t did_stall;
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uint8_t bulk_or_control;
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};
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struct dwc_otg_config_desc {
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struct usb_config_descriptor confd;
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struct usb_interface_descriptor ifcd;
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struct usb_endpoint_descriptor endpd;
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} __packed;
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union dwc_otg_hub_temp {
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uWord wValue;
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struct usb_port_status ps;
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};
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struct dwc_otg_flags {
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uint8_t change_connect:1;
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uint8_t change_suspend:1;
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uint8_t change_reset:1;
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uint8_t change_enabled:1;
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uint8_t change_over_current:1;
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uint8_t status_suspend:1; /* set if suspended */
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uint8_t status_vbus:1; /* set if present */
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uint8_t status_bus_reset:1; /* set if reset complete */
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uint8_t status_high_speed:1; /* set if High Speed is selected */
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uint8_t status_low_speed:1; /* set if Low Speed is selected */
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uint8_t status_device_mode:1; /* set if device mode */
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uint8_t self_powered:1;
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uint8_t clocks_off:1;
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uint8_t port_powered:1;
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uint8_t port_enabled:1;
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uint8_t port_over_current:1;
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uint8_t d_pulled_up:1;
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};
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struct dwc_otg_profile {
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struct usb_hw_ep_profile usb;
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uint16_t max_buffer;
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};
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struct dwc_otg_chan_state {
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uint16_t allocated;
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uint16_t wait_sof;
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uint32_t hcint;
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uint16_t tx_p_size; /* periodic */
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uint16_t tx_np_size; /* non-periodic */
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};
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struct dwc_otg_softc {
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struct usb_bus sc_bus;
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union dwc_otg_hub_temp sc_hub_temp;
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struct dwc_otg_profile sc_hw_ep_profile[DWC_OTG_MAX_ENDPOINTS];
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struct usb_callout sc_timer;
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struct usb_device *sc_devices[DWC_OTG_MAX_DEVICES];
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struct resource *sc_io_res;
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struct resource *sc_irq_res;
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void *sc_intr_hdl;
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bus_size_t sc_io_size;
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bus_space_tag_t sc_io_tag;
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bus_space_handle_t sc_io_hdl;
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uint32_t sc_rx_bounce_buffer[1024 / 4];
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uint32_t sc_tx_bounce_buffer[MAX(512 * DWC_OTG_MAX_TXP, 1024) / 4];
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uint32_t sc_fifo_size;
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uint32_t sc_tx_max_size;
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uint32_t sc_tx_cur_p_level; /* periodic */
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uint32_t sc_tx_cur_np_level; /* non-periodic */
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uint32_t sc_irq_mask;
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uint32_t sc_last_rx_status;
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uint32_t sc_out_ctl[DWC_OTG_MAX_ENDPOINTS];
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uint32_t sc_in_ctl[DWC_OTG_MAX_ENDPOINTS];
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struct dwc_otg_chan_state sc_chan_state[DWC_OTG_MAX_CHANNELS];
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uint32_t sc_tmr_val;
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uint32_t sc_hprt_val;
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uint16_t sc_active_rx_ep;
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uint16_t sc_last_frame_num;
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uint8_t sc_timer_active;
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uint8_t sc_dev_ep_max;
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uint8_t sc_dev_in_ep_max;
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uint8_t sc_host_ch_max;
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uint8_t sc_needsof;
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uint8_t sc_rt_addr; /* root HUB address */
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uint8_t sc_conf; /* root HUB config */
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uint8_t sc_mode; /* mode of operation */
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#define DWC_MODE_OTG 0 /* both modes */
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#define DWC_MODE_DEVICE 1 /* device only */
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#define DWC_MODE_HOST 2 /* host only */
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uint8_t sc_hub_idata[1];
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struct dwc_otg_flags sc_flags;
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};
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/* prototypes */
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void dwc_otg_interrupt(struct dwc_otg_softc *);
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int dwc_otg_init(struct dwc_otg_softc *);
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void dwc_otg_uninit(struct dwc_otg_softc *);
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#endif /* _DWC_OTG_H_ */
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