167aa83312
This driver was written by Myson and is made available by their courtesy. The 5.x version is not fully tested (I will be testing) but the 4.x version has been tested by many. I will commit it soon. Myson have their own chip design based on the DEC 214xx family but with several differences. Myson sells this chip to several EOMs in teh Chinese area so there may be many noname brand cards that respond to this driver. Myson will be supplying a list of some of these.
586 lines
22 KiB
C
586 lines
22 KiB
C
/*
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* Copyright (c) 2002 Myson Technology Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/
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*
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* $FreeBSD$
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*
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* Myson MTD80x register definitions.
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*
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*/
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#define MY_PAR0 0x0 /* physical address 0-3 */
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#define MY_PAR1 0x04 /* physical address 4-5 */
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#define MY_MAR0 0x08 /* multicast address 0-3 */
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#define MY_MAR1 0x0C /* multicast address 4-7 */
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#define MY_FAR0 0x10 /* flow-control address 0-3 */
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#define MY_FAR1 0x14 /* flow-control address 4-5 */
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#define MY_TCRRCR 0x18 /* receive & transmit configuration */
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#define MY_BCR 0x1C /* bus command */
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#define MY_TXPDR 0x20 /* transmit polling demand */
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#define MY_RXPDR 0x24 /* receive polling demand */
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#define MY_RXCWP 0x28 /* receive current word pointer */
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#define MY_TXLBA 0x2C /* transmit list base address */
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#define MY_RXLBA 0x30 /* receive list base address */
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#define MY_ISR 0x34 /* interrupt status */
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#define MY_IMR 0x38 /* interrupt mask */
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#define MY_FTH 0x3C /* flow control high/low threshold */
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#define MY_MANAGEMENT 0x40 /* bootrom/eeprom and mii management */
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#define MY_TALLY 0x44 /* tally counters for crc and mpa */
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#define MY_TSR 0x48 /* tally counter for transmit status */
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#define MY_PHYBASE 0x4c
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/*
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* Receive Configuration Register
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*/
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#define MY_RXRUN 0x00008000 /* receive running status */
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#define MY_EIEN 0x00004000 /* early interrupt enable */
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#define MY_RFCEN 0x00002000 /* receive flow control packet enable */
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#define MY_NDFA 0x00001000 /* not defined flow control address */
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#define MY_RBLEN 0x00000800 /* receive burst length enable */
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#define MY_RPBLE1 0x00000000 /* 1 word */
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#define MY_RPBLE4 0x00000100 /* 4 words */
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#define MY_RPBLE8 0x00000200 /* 8 words */
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#define MY_RPBLE16 0x00000300 /* 16 words */
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#define MY_RPBLE32 0x00000400 /* 32 words */
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#define MY_RPBLE64 0x00000500 /* 64 words */
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#define MY_RPBLE128 0x00000600 /* 128 words */
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#define MY_RPBLE512 0x00000700 /* 512 words */
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#define MY_PROM 0x000000080 /* promiscuous mode */
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#define MY_AB 0x000000040 /* accept broadcast */
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#define MY_AM 0x000000020 /* accept mutlicast */
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#define MY_ARP 0x000000008 /* receive runt pkt */
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#define MY_ALP 0x000000004 /* receive long pkt */
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#define MY_SEP 0x000000002 /* receive error pkt */
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#define MY_RE 0x000000001 /* receive enable */
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/*
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* Transmit Configuration Register
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*/
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#define MY_TXRUN 0x04000000 /* transmit running status */
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#define MY_Enhanced 0x02000000 /* transmit enhanced mode */
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#define MY_TFCEN 0x01000000 /* tx flow control packet enable */
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#define MY_TFT64 0x00000000 /* 64 bytes */
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#define MY_TFT32 0x00200000 /* 32 bytes */
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#define MY_TFT128 0x00400000 /* 128 bytes */
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#define MY_TFT256 0x00600000 /* 256 bytes */
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#define MY_TFT512 0x00800000 /* 512 bytes */
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#define MY_TFT768 0x00A00000 /* 768 bytes */
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#define MY_TFT1024 0x00C00000 /* 1024 bytes */
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#define MY_TFTSF 0x00E00000 /* store and forward */
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#define MY_FD 0x00100000 /* full duplex mode */
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#define MY_PS10 0x00080000 /* port speed is 10M */
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#define MY_TE 0x00040000 /* transmit enable */
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#define MY_PS1000 0x00010000 /* port speed is 1000M */
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/*
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* Bus Command Register
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*/
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#define MY_PROG 0x00000200 /* programming */
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#define MY_RLE 0x00000100 /* read line command enable */
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#define MY_RME 0x00000080 /* read multiple command enable */
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#define MY_WIE 0x00000040 /* write and invalidate cmd enable */
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#define MY_PBL1 0x00000000 /* 1 dword */
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#define MY_PBL4 0x00000008 /* 4 dwords */
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#define MY_PBL8 0x00000010 /* 8 dwords */
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#define MY_PBL16 0x00000018 /* 16 dwords */
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#define MY_PBL32 0x00000020 /* 32 dwords */
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#define MY_PBL64 0x00000028 /* 64 dwords */
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#define MY_PBL128 0x00000030 /* 128 dwords */
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#define MY_PBL512 0x00000038 /* 512 dwords */
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#define MY_ABR 0x00000004 /* arbitration rule */
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#define MY_BLS 0x00000002 /* big/little endian select */
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#define MY_SWR 0x00000001 /* software reset */
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/*
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* Transmit Poll Demand Register
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*/
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#define MY_TxPollDemand 0x1
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/*
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* Receive Poll Demand Register
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*/
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#define MY_RxPollDemand 0x01
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/*
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* Interrupt Status Register
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*/
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#define MY_RFCON 0x00020000 /* receive flow control xon packet */
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#define MY_RFCOFF 0x00010000 /* receive flow control xoff packet */
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#define MY_LSCStatus 0x00008000 /* link status change */
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#define MY_ANCStatus 0x00004000 /* autonegotiation completed */
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#define MY_FBE 0x00002000 /* fatal bus error */
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#define MY_FBEMask 0x00001800
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#define MY_ParityErr 0x00000000 /* parity error */
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#define MY_MasterErr 0x00000800 /* master error */
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#define MY_TargetErr 0x00001000 /* target abort */
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#define MY_TUNF 0x00000400 /* transmit underflow */
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#define MY_ROVF 0x00000200 /* receive overflow */
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#define MY_ETI 0x00000100 /* transmit early int */
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#define MY_ERI 0x00000080 /* receive early int */
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#define MY_CNTOVF 0x00000040 /* counter overflow */
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#define MY_RBU 0x00000020 /* receive buffer unavailable */
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#define MY_TBU 0x00000010 /* transmit buffer unavilable */
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#define MY_TI 0x00000008 /* transmit interrupt */
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#define MY_RI 0x00000004 /* receive interrupt */
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#define MY_RxErr 0x00000002 /* receive error */
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/*
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* Interrupt Mask Register
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*/
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#define MY_MRFCON 0x00020000 /* receive flow control xon packet */
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#define MY_MRFCOFF 0x00010000 /* receive flow control xoff packet */
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#define MY_MLSCStatus 0x00008000 /* link status change */
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#define MY_MANCStatus 0x00004000 /* autonegotiation completed */
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#define MY_MFBE 0x00002000 /* fatal bus error */
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#define MY_MFBEMask 0x00001800
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#define MY_MTUNF 0x00000400 /* transmit underflow */
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#define MY_MROVF 0x00000200 /* receive overflow */
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#define MY_METI 0x00000100 /* transmit early int */
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#define MY_MERI 0x00000080 /* receive early int */
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#define MY_MCNTOVF 0x00000040 /* counter overflow */
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#define MY_MRBU 0x00000020 /* receive buffer unavailable */
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#define MY_MTBU 0x00000010 /* transmit buffer unavilable */
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#define MY_MTI 0x00000008 /* transmit interrupt */
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#define MY_MRI 0x00000004 /* receive interrupt */
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#define MY_MRxErr 0x00000002 /* receive error */
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/* 90/1/18 delete */
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/* #define MY_INTRS MY_FBE|MY_MRBU|MY_TBU|MY_MTI|MY_MRI|MY_METI */
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#define MY_INTRS MY_MRBU|MY_TBU|MY_MTI|MY_MRI|MY_METI
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/*
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* Flow Control High/Low Threshold Register
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*/
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#define MY_FCHTShift 16 /* flow control high threshold */
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#define MY_FCLTShift 0 /* flow control low threshold */
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/*
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* BootROM/EEPROM/MII Management Register
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*/
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#define MY_MASK_MIIR_MII_READ 0x00000000
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#define MY_MASK_MIIR_MII_WRITE 0x00000008
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#define MY_MASK_MIIR_MII_MDO 0x00000004
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#define MY_MASK_MIIR_MII_MDI 0x00000002
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#define MY_MASK_MIIR_MII_MDC 0x00000001
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/*
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* Tally Counter for CRC and MPA
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*/
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#define MY_TCOVF 0x80000000 /* crc tally counter overflow */
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#define MY_CRCMask 0x7fff0000 /* crc number: bit 16-30 */
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#define MY_CRCShift 16
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#define MY_TMOVF 0x00008000 /* mpa tally counter overflow */
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#define MY_MPAMask 0x00007fff /* mpa number: bit 0-14 */
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#define MY_MPAShift 0
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/*
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* Tally Counters for transmit status
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*/
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#define MY_AbortMask 0xff000000 /* transmit abort number */
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#define MY_AbortShift 24
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#define MY_LColMask 0x00ff0000 /* transmit late collisions */
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#define MY_LColShift 16
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#define MY_NCRMask 0x0000ffff /* transmit retry number */
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#define MY_NCRShift 0
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/*
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* Myson TX/RX descriptor structure.
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*/
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struct my_desc {
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u_int32_t my_status;
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u_int32_t my_ctl;
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u_int32_t my_data;
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u_int32_t my_next;
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};
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/*
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* for tx/rx descriptors
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*/
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#define MY_OWNByNIC 0x80000000
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#define MY_OWNByDriver 0x0
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/*
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* receive descriptor 0
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*/
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#define MY_RXOWN 0x80000000 /* own bit */
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#define MY_FLNGMASK 0x0fff0000 /* frame length */
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#define MY_FLNGShift 16
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#define MY_MARSTATUS 0x00004000 /* multicast address received */
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#define MY_BARSTATUS 0x00002000 /* broadcast address received */
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#define MY_PHYSTATUS 0x00001000 /* physical address received */
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#define MY_RXFSD 0x00000800 /* first descriptor */
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#define MY_RXLSD 0x00000400 /* last descriptor */
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#define MY_ES 0x00000080 /* error summary */
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#define MY_RUNT 0x00000040 /* runt packet received */
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#define MY_LONG 0x00000020 /* long packet received */
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#define MY_FAE 0x00000010 /* frame align error */
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#define MY_CRC 0x00000008 /* crc error */
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#define MY_RXER 0x00000004 /* receive error */
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#define MY_RDES0CHECK 0x000078fc /* only check MAR, BAR, PHY, ES, RUNT,
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LONG, FAE, CRC and RXER bits */
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/*
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* receive descriptor 1
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*/
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#define MY_RXIC 0x00800000 /* interrupt control */
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#define MY_RBSMASK 0x000007ff /* receive buffer size */
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#define MY_RBSShift 0
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/*
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* transmit descriptor 0
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*/
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#define MY_TXERR 0x00008000 /* transmit error */
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#define MY_JABTO 0x00004000 /* jabber timeout */
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#define MY_CSL 0x00002000 /* carrier sense lost */
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#define MY_LC 0x00001000 /* late collision */
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#define MY_EC 0x00000800 /* excessive collision */
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#define MY_UDF 0x00000400 /* fifo underflow */
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#define MY_DFR 0x00000200 /* deferred */
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#define MY_HF 0x00000100 /* heartbeat fail */
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#define MY_NCRMASK 0x000000ff /* collision retry count */
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#define MY_NCRShift 0
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/*
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* tx descriptor 1
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*/
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#define MY_TXIC 0x80000000 /* interrupt control */
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#define MY_ETIControl 0x40000000 /* early transmit interrupt */
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#define MY_TXLD 0x20000000 /* last descriptor */
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#define MY_TXFD 0x10000000 /* first descriptor */
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#define MY_CRCDisable 0x00000000 /* crc control */
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#define MY_CRCEnable 0x08000000
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#define MY_PADDisable 0x00000000 /* padding control */
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#define MY_PADEnable 0x04000000
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#define MY_RetryTxLC 0x02000000 /* retry late collision */
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#define MY_PKTShift 11 /* transmit pkt size */
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#define MY_TBSMASK 0x000007ff
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#define MY_TBSShift 0 /* transmit buffer size */
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#define MY_MAXFRAGS 1
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#define MY_RX_LIST_CNT 64
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#define MY_TX_LIST_CNT 64
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#define MY_MIN_FRAMELEN 60
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/*
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* A transmit 'super descriptor' is actually MY_MAXFRAGS regular
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* descriptors clumped together. The idea here is to emulate the
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* multi-fragment descriptor layout found in devices such as the
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* Texas Instruments ThunderLAN and 3Com boomerang and cylone chips.
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* The advantage to using this scheme is that it avoids buffer copies.
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* The disadvantage is that there's a certain amount of overhead due
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* to the fact that each 'fragment' is 16 bytes long. In my tests,
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* this limits top speed to about 10.5MB/sec. It should be more like
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* 11.5MB/sec. However, the upshot is that you can achieve better
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* results on slower machines: a Pentium 200 can pump out packets at
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* same speed as a PII 400.
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*/
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struct my_txdesc {
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struct my_desc my_frag[MY_MAXFRAGS];
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};
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#define MY_TXSTATUS(x) x->my_ptr->my_frag[x->my_lastdesc].my_status
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#define MY_TXCTL(x) x->my_ptr->my_frag[x->my_lastdesc].my_ctl
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#define MY_TXDATA(x) x->my_ptr->my_frag[x->my_lastdesc].my_data
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#define MY_TXNEXT(x) x->my_ptr->my_frag[x->my_lastdesc].my_next
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#define MY_TXOWN(x) x->my_ptr->my_frag[0].my_status
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#define MY_UNSENT 0x1234
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struct my_list_data {
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struct my_desc my_rx_list[MY_RX_LIST_CNT];
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struct my_txdesc my_tx_list[MY_TX_LIST_CNT];
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};
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struct my_chain {
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struct my_txdesc *my_ptr;
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struct mbuf *my_mbuf;
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struct my_chain *my_nextdesc;
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u_int8_t my_lastdesc;
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};
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struct my_chain_onefrag {
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struct my_desc *my_ptr;
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struct mbuf *my_mbuf;
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struct my_chain_onefrag *my_nextdesc;
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u_int8_t my_rlast;
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};
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struct my_chain_data {
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struct my_chain_onefrag my_rx_chain[MY_RX_LIST_CNT];
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struct my_chain my_tx_chain[MY_TX_LIST_CNT];
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struct my_chain_onefrag *my_rx_head;
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struct my_chain *my_tx_head;
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struct my_chain *my_tx_tail;
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struct my_chain *my_tx_free;
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};
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struct my_type {
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u_int16_t my_vid;
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u_int16_t my_did;
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char *my_name;
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};
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#define MY_FLAG_FORCEDELAY 1
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#define MY_FLAG_SCHEDDELAY 2
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#define MY_FLAG_DELAYTIMEO 3
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struct my_softc {
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struct arpcom arpcom; /* interface info */
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struct ifmedia ifmedia; /* media info */
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bus_space_handle_t my_bhandle;
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bus_space_tag_t my_btag;
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struct my_type *my_info; /* adapter info */
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struct my_type *my_pinfo; /* phy info */
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struct resource *my_res;
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struct resource *my_irq;
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void *my_intrhand;
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u_int8_t my_unit; /* interface number */
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u_int8_t my_phy_addr; /* PHY address */
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u_int8_t my_tx_pend; /* TX pending */
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u_int8_t my_want_auto;
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u_int8_t my_autoneg;
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u_int16_t my_txthresh;
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u_int8_t my_stats_no_timeout;
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caddr_t my_ldata_ptr;
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struct my_list_data *my_ldata;
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struct my_chain_data my_cdata;
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device_t my_miibus;
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struct callout_handle my_stat_ch;
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/* Add by Surfer 2001/12/2 */
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struct mtx my_mtx;
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};
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/* Add by Surfer 2001/12/2 */
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#define MY_LOCK(_sc) mtx_lock(&(_sc)->my_mtx)
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#define MY_UNLOCK(_sc) mtx_unlock(&(_sc)->my_mtx)
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/*
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* register space access macros
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*/
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4(sc->my_btag, sc->my_bhandle, reg, val)
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#define CSR_WRITE_2(sc, reg, val) \
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bus_space_write_2(sc->my_btag, sc->my_bhandle, reg, val)
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#define CSR_WRITE_1(sc, reg, val) \
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bus_space_write_1(sc->my_btag, sc->my_bhandle, reg, val)
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4(sc->my_btag, sc->my_bhandle, reg)
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#define CSR_READ_2(sc, reg) \
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bus_space_read_2(sc->my_btag, sc->my_bhandle, reg)
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#define CSR_READ_1(sc, reg) \
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bus_space_read_1(sc->my_btag, sc->my_bhandle, reg)
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#define MY_TIMEOUT 1000
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/*
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* General constants that are fun to know.
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*
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* MYSON PCI vendor ID
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*/
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#define MYSONVENDORID 0x1516
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/*
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* MYSON device IDs.
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*/
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#define MTD800ID 0x0800
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#define MTD803ID 0x0803
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#define MTD891ID 0x0891
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/*
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* ST+OP+PHYAD+REGAD+TA
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*/
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#define MY_OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
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#define MY_OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
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/*
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* Constansts for Myson PHY
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*/
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#define MysonPHYID0 0x0300
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/*
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* Constansts for Seeq 80225 PHY
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*/
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#define SeeqPHYID0 0x0016
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#define SEEQ_MIIRegister18 18
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#define SEEQ_SPD_DET_100 0x80
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#define SEEQ_DPLX_DET_FULL 0x40
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/*
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* Constansts for Ahdoc 101 PHY
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*/
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|
#define AhdocPHYID0 0x0022
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|
#define AHDOC_DiagnosticReg 18
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#define AHDOC_DPLX_FULL 0x0800
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#define AHDOC_Speed_100 0x0400
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|
|
|
/*
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|
* Constansts for Marvell 88E1000/88E1000S PHY and LevelOne PHY
|
|
*/
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|
#define MarvellPHYID0 0x0141
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|
#define LevelOnePHYID0 0x0013
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|
|
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#define Marvell_SpecificStatus 17
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|
#define Marvell_Speed1000 0x8000
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|
#define Marvell_Speed100 0x4000
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#define Marvell_FullDuplex 0x2000
|
|
|
|
/*
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|
* PCI low memory base and low I/O base register, and
|
|
* other PCI registers. Note: some are only available on
|
|
* the 3c905B, in particular those that related to power management.
|
|
*/
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|
#define MY_PCI_VENDOR_ID 0x00
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|
#define MY_PCI_DEVICE_ID 0x02
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|
#define MY_PCI_COMMAND 0x04
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#define MY_PCI_STATUS 0x06
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|
#define MY_PCI_CLASSCODE 0x09
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#define MY_PCI_LATENCY_TIMER 0x0D
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|
#define MY_PCI_HEADER_TYPE 0x0E
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|
#define MY_PCI_LOIO 0x10
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|
#define MY_PCI_LOMEM 0x14
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|
#define MY_PCI_BIOSROM 0x30
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|
#define MY_PCI_INTLINE 0x3C
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|
#define MY_PCI_INTPIN 0x3D
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|
#define MY_PCI_MINGNT 0x3E
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|
#define MY_PCI_MINLAT 0x0F
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|
#define MY_PCI_RESETOPT 0x48
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|
#define MY_PCI_EEPROM_DATA 0x4C
|
|
|
|
#define PHY_UNKNOWN 3
|
|
|
|
#define MY_PHYADDR_MIN 0x00
|
|
#define MY_PHYADDR_MAX 0x1F
|
|
|
|
#define PHY_BMCR 0x00
|
|
#define PHY_BMSR 0x01
|
|
#define PHY_VENID 0x02
|
|
#define PHY_DEVID 0x03
|
|
#define PHY_ANAR 0x04
|
|
#define PHY_LPAR 0x05
|
|
#define PHY_ANEXP 0x06
|
|
#define PHY_NPTR 0x07
|
|
#define PHY_LPNPR 0x08
|
|
#define PHY_1000CR 0x09
|
|
#define PHY_1000SR 0x0a
|
|
|
|
#define PHY_ANAR_NEXTPAGE 0x8000
|
|
#define PHY_ANAR_RSVD0 0x4000
|
|
#define PHY_ANAR_TLRFLT 0x2000
|
|
#define PHY_ANAR_RSVD1 0x1000
|
|
#define PHY_ANAR_RSVD2 0x0800
|
|
#define PHY_ANAR_RSVD3 0x0400
|
|
#define PHY_ANAR_100BT4 0x0200L
|
|
#define PHY_ANAR_100BTXFULL 0x0100
|
|
#define PHY_ANAR_100BTXHALF 0x0080
|
|
#define PHY_ANAR_10BTFULL 0x0040
|
|
#define PHY_ANAR_10BTHALF 0x0020
|
|
#define PHY_ANAR_PROTO4 0x0010
|
|
#define PHY_ANAR_PROTO3 0x0008
|
|
#define PHY_ANAR_PROTO2 0x0004
|
|
#define PHY_ANAR_PROTO1 0x0002
|
|
#define PHY_ANAR_PROTO0 0x0001
|
|
|
|
#define PHY_1000SR_1000BTXFULL 0x0800
|
|
#define PHY_1000SR_1000BTXHALF 0x0400
|
|
|
|
/*
|
|
* These are the register definitions for the PHY (physical layer
|
|
* interface chip).
|
|
*/
|
|
/*
|
|
* PHY BMCR Basic Mode Control Register
|
|
*/
|
|
#define PHY_BMCR_RESET 0x8000
|
|
#define PHY_BMCR_LOOPBK 0x4000
|
|
#define PHY_BMCR_SPEEDSEL 0x2000
|
|
#define PHY_BMCR_AUTONEGENBL 0x1000
|
|
#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
|
|
#define PHY_BMCR_ISOLATE 0x0400
|
|
#define PHY_BMCR_AUTONEGRSTR 0x0200
|
|
#define PHY_BMCR_DUPLEX 0x0100
|
|
#define PHY_BMCR_COLLTEST 0x0080
|
|
#define PHY_BMCR_1000 0x0040 /* only used for Marvell PHY */
|
|
#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
|
|
|
|
/*
|
|
* RESET: 1 == software reset, 0 == normal operation
|
|
* Resets status and control registers to default values.
|
|
* Relatches all hardware config values.
|
|
*
|
|
* LOOPBK: 1 == loopback operation enabled, 0 == normal operation
|
|
*
|
|
* SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
|
|
* Link speed is selected byt his bit or if auto-negotiation if bit
|
|
* 12 (AUTONEGENBL) is set (in which case the value of this register
|
|
* is ignored).
|
|
*
|
|
* AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
|
|
* Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
|
|
* determine speed and mode. Should be cleared and then set if PHY configured
|
|
* for no autoneg on startup.
|
|
*
|
|
* ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
|
|
*
|
|
* AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
|
|
*
|
|
* DUPLEX: 1 == full duplex mode, 0 == half duplex mode
|
|
*
|
|
* COLLTEST: 1 == collision test enabled, 0 == normal operation
|
|
*/
|
|
|
|
/*
|
|
* PHY, BMSR Basic Mode Status Register
|
|
*/
|
|
#define PHY_BMSR_100BT4 0x8000
|
|
#define PHY_BMSR_100BTXFULL 0x4000
|
|
#define PHY_BMSR_100BTXHALF 0x2000
|
|
#define PHY_BMSR_10BTFULL 0x1000
|
|
#define PHY_BMSR_10BTHALF 0x0800
|
|
#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
|
|
#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
|
|
#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
|
|
#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
|
|
#define PHY_BMSR_MFPRESUP 0x0040
|
|
#define PHY_BMSR_AUTONEGCOMP 0x0020
|
|
#define PHY_BMSR_REMFAULT 0x0010
|
|
#define PHY_BMSR_CANAUTONEG 0x0008
|
|
#define PHY_BMSR_LINKSTAT 0x0004
|
|
#define PHY_BMSR_JABBER 0x0002
|
|
#define PHY_BMSR_EXTENDED 0x0001
|
|
|
|
|