591f4054cb
It currently supports the PMC Sierra Lite, Ultra and 622 chips and the IDT 77105. The driver handles media options and state in a consistent manner for ATM drivers. The next commit to the midway driver will make it use utopia.
120 lines
5.1 KiB
C
120 lines
5.1 KiB
C
/*
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* Copyright (c) 2003
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* Fraunhofer Institute for Open Communication Systems (FhG Fokus).
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Author: Hartmut Brandt <harti@freebsd.org>
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*
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* $FreeBSD$
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*
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* Register definitions for the following chips:
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* IDT 77105
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*/
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#ifndef _DEV_UTOPIA_IDTPHY_H
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#define _DEV_UTOPIA_IDTPHY_H
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#define IDTPHY_REGO_MCR 0x00
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#define IDTPHY_REGN_MCR "Master Control Register"
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#define IDTPHY_REGX_MCR "\020\010UPLO\7DREC\6ECEI\5TDPC\4DRIC\3HALTTX\2BYTEM\1EI"
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#define IDTPHY_REGM_MCR_UPL0 0x80
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#define IDTPHY_REGM_MCR_DREC 0x40
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#define IDTPHY_REGM_MCR_ECEI 0x20
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#define IDTPHY_REGM_MCR_TDPC 0x10
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#define IDTPHY_REGM_MCR_DRIC 0x08
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#define IDTPHY_REGM_MCR_HALTTX 0x04
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#define IDTPHY_REGM_MCR_BYTEM 0x02
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#define IDTPHY_REGM_MCR_EI 0x01
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#define IDTPHY_REGO_ISTAT 0x01
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#define IDTPHY_REGN_ISTAT "Interrupt Status"
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#define IDTPHY_REGX_ISTAT "\020\7GOOD\6HECE\5SCRE\4TPE\3RSCC\2RSE\1RFO"
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#define IDTPHY_REGM_ISTAT_GOOD 0x40 /* good signal bit */
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#define IDTPHY_REGM_ISTAT_HECE 0x20 /* HEC error */
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#define IDTPHY_REGM_ISTAT_SCRE 0x10 /* short cell received error */
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#define IDTPHY_REGM_ISTAT_TPE 0x08 /* transmit parity error */
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#define IDTPHY_REGM_ISTAT_RSCC 0x04 /* receive signal condition change */
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#define IDTPHY_REGM_ISTAT_RSE 0x02 /* receive symbol error */
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#define IDTPHY_REGM_ISTAT_RFO 0x01 /* read FIFO overrun */
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#define IDTPHY_REGO_DIAG 0x02
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#define IDTPHY_REGN_DIAG "Diagnostic Control"
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#define IDTPHY_REGX_DIAG "\020\010FTD\7ROS\6MULTI\5RFLUSH\4ITPE\3IHECE\11\3\0NORM\11\3\2PLOOP\11\3\3LLOOP"
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#define IDTPHY_REGM_DIAG_FTD 0x80 /* Force TxClav Deassert */
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#define IDTPHY_REGM_DIAG_ROS 0x40 /* RxClav Operation Select */
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#define IDTPHY_REGM_DIAG_MULTI 0x20 /* Multi-phy operation */
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#define IDTPHY_REGM_DIAG_RFLUSH 0x10 /* clear receive Fifo */
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#define IDTPHY_REGM_DIAG_ITPE 0x08 /* insert transmit payload error */
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#define IDTPHY_REGM_DIAG_IHECE 0x04 /* insert transmit HEC error */
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#define IDTPHY_REGM_DIAG_LOOP 0x03 /* loopback mode */
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#define IDTPHY_REGM_DIAG_LOOP_NONE 0x00 /* normal */
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#define IDTPHY_REGM_DIAG_LOOP_PHY 0x02 /* PHY loopback */
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#define IDTPHY_REGM_DIAG_LOOP_LINE 0x03 /* Line loopback */
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#define IDTPHY_REGO_LHEC 0x03
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#define IDTPHY_REGN_LHEC "LED Driver and HEC Status/Control"
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#define IDTPHY_REGX_LHEC "\020\7DRHEC\6DTHEC\11\x18\0CYC1\11\x18\1CYC2\11\x18\2CYC4\11\x18\3CYC8\3FIFOE\2TXLED\1RXLED"
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#define IDTPHY_REGM_LHEC_DRHEC 0x40 /* disable receive HEC */
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#define IDTPHY_REGM_LHEC_DTHEC 0x20 /* disable transmit HEC */
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#define IDTPHY_REGM_LHEC_RXREF 0x18 /* RxRef pulse width */
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#define IDTPHY_REGM_LHEC_RXREF1 0x00 /* 1 pulse */
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#define IDTPHY_REGM_LHEC_RXREF2 0x08 /* 2 pulse */
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#define IDTPHY_REGM_LHEC_RXREF4 0x10 /* 4 pulse */
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#define IDTPHY_REGM_LHEC_RXREF8 0x18 /* 8 pulse */
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#define IDTPHY_REGM_LHEC_FIFOE 0x04 /* Fifo empty */
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#define IDTPHY_REGM_LHEC_TXLED 0x02 /* Tx LED status */
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#define IDTPHY_REGM_LHEC_RXLED 0x01 /* Rx LED status */
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#define IDTPHY_REGO_CNT 0x04 /* +0x05 */
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#define IDTPHY_REGN_CNT "Counter"
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#define IDTPHY_REGO_CNTS 0x06
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#define IDTPHY_REGN_CNTS "Counter select"
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#define IDTPHY_REGX_CNTS "\020\4SEC\3TX\2RX\1HECE"
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#define IDTPHY_REGM_CNTS_SEC 0x08 /* symbol error counter */
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#define IDTPHY_REGM_CNTS_TX 0x04 /* Tx cells */
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#define IDTPHY_REGM_CNTS_RX 0x02 /* Rx cells */
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#define IDTPHY_REGM_CNTS_HECE 0x01 /* HEC errors */
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#define IDTPHY_PRINT_77105 \
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{ /* 00 */ \
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UTP_REGT_BITS, IDTPHY_REGO_MCR, \
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IDTPHY_REGN_MCR, IDTPHY_REGX_MCR }, \
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{ /* 01 */ \
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UTP_REGT_BITS, IDTPHY_REGO_ISTAT, \
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IDTPHY_REGN_ISTAT, IDTPHY_REGX_ISTAT }, \
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{ /* 02 */ \
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UTP_REGT_BITS, IDTPHY_REGO_DIAG, \
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IDTPHY_REGN_DIAG, IDTPHY_REGX_DIAG }, \
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{ /* 03 */ \
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UTP_REGT_BITS, IDTPHY_REGO_LHEC, \
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IDTPHY_REGN_LHEC, IDTPHY_REGX_LHEC }, \
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{ /* 04, 05 */ \
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UTP_REGT_INT16, IDTPHY_REGO_CNT, \
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IDTPHY_REGN_CNT, NULL }, \
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{ /* 06 */ \
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UTP_REGT_BITS, IDTPHY_REGO_CNTS, \
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IDTPHY_REGN_CNTS, IDTPHY_REGX_CNTS }
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#endif /* _DEV_UTOPIA_IDTPHY_H */
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