1495 lines
34 KiB
C
1495 lines
34 KiB
C
/*
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* Copyright (c) 1996, by Steve Passe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: mp_machdep.c,v 1.6 1997/05/01 19:27:58 fsmp Exp $
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*/
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#include "opt_smp.h"
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#define FIX_MP_TABLE_WORKS
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#include "opt_serial.h"
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#include <sys/param.h> /* for KERNBASE */
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#include <sys/types.h>
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#include <sys/sysproto.h>
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#include <sys/time.h>
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#include <sys/systm.h>
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#include <vm/vm.h> /* for KERNBASE */
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#include <vm/vm_param.h> /* for KERNBASE */
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#include <vm/pmap.h> /* for KERNBASE */
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#include <machine/pmap.h> /* for KERNBASE */
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#include <machine/smp.h>
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#include <machine/apic.h>
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#include <machine/mpapic.h>
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#include <machine/cpufunc.h>
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#include <machine/segments.h>
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#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG */
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#include <i386/i386/cons.h> /* cngetc() */
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#if defined(APIC_IO)
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#include <i386/include/md_var.h> /* setidt() */
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#include <i386/isa/icu.h> /* Xinvltlb() */
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#include <i386/isa/isa_device.h> /* Xinvltlb() */
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#endif /* APIC_IO */
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#define WARMBOOT_TARGET 0
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#define WARMBOOT_OFF (KERNBASE + 0x0467)
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#define WARMBOOT_SEG (KERNBASE + 0x0469)
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#define BIOS_BASE (0xf0000)
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#define BIOS_SIZE (0x10000)
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#define BIOS_COUNT (BIOS_SIZE/4)
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#define CMOS_REG (0x70)
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#define CMOS_DATA (0x71)
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#define BIOS_RESET (0x0f)
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#define BIOS_WARM (0x0a)
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/*
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* this code MUST be enabled here and in mpboot.s.
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* it follows the very early stages of AP boot by placing values in CMOS ram.
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* it NORMALLY will never be needed and thus the primitive method for enabling.
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*
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#define CHECK_POINTS
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*/
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#if defined(CHECK_POINTS)
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#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
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#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
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#define CHECK_INIT(D); \
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CHECK_WRITE(0x34, (D)); \
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CHECK_WRITE(0x35, (D)); \
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CHECK_WRITE(0x36, (D)); \
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CHECK_WRITE(0x37, (D)); \
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CHECK_WRITE(0x38, (D)); \
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CHECK_WRITE(0x39, (D));
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#define CHECK_PRINT(S); \
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printf("%s: %d, %d, %d, %d, %d, %d\n", \
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(S), \
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CHECK_READ(0x34), \
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CHECK_READ(0x35), \
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CHECK_READ(0x36), \
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CHECK_READ(0x37), \
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CHECK_READ(0x38), \
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CHECK_READ(0x39));
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#else /* CHECK_POINTS */
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#define CHECK_INIT(D)
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#define CHECK_PRINT(S)
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#endif /* CHECK_POINTS */
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/** FIXME: what system files declare these??? */
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extern struct region_descriptor r_gdt, r_idt;
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/* global data */
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struct proc *SMPcurproc[NCPU];
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struct pcb *SMPcurpcb[NCPU];
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struct timeval SMPruntime[NCPU];
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int mp_ncpus; /* # of CPUs, including BSP */
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int mp_naps; /* # of Applications processors */
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int mp_nbusses; /* # of busses */
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int mp_napics; /* # of IO APICs */
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int mpenabled;
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int boot_cpu_id; /* designated BSP */
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vm_offset_t cpu_apic_address;
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vm_offset_t io_apic_address[NAPIC];
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u_int32_t cpu_apic_versions[NCPU];
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u_int32_t io_apic_versions[NAPIC];
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/*
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* APIC ID logical/physical mapping structures
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*/
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int cpu_num_to_apic_id[NCPU];
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int io_num_to_apic_id[NAPIC];
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int apic_id_to_logical[NAPICID];
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/*
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* look for MP compliant motherboard.
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*/
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static u_int boot_address;
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static u_int base_memory;
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static int picmode; /* 0: virtual wire mode, 1: PIC mode */
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static u_int mpfps;
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static int search_for_sig(u_int32_t target, int count);
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static int mp_probe(u_int base_top);
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static void mp_enable(u_int boot_addr);
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/*
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* calculate usable address in base memory for AP trampoline code
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*/
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u_int
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mp_bootaddress(u_int basemem)
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{
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base_memory = basemem * 1024; /* convert to bytes */
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boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
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if ((base_memory - boot_address) < bootMP_size)
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boot_address -= 4096; /* not enough, lower by 4k */
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return boot_address;
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}
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/*
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* startup the SMP processors
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*/
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void
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mp_start(void)
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{
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/* look for MP capable motherboard */
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if (mp_probe(base_memory))
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mp_enable(boot_address);
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else {
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printf("MP FPS NOT FOUND, suggest use of 'mptable' program\n");
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panic("can't continue!\n");
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}
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/* finish pmap initialization - turn off V==P mapping at zero */
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pmap_bootstrap2();
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}
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/*
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* print various information about the SMP system hardware and setup
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*/
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void
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mp_announce(void)
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{
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int x;
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printf("FreeBSD/SMP: Multiprocessor motherboard\n");
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printf(" cpu0 (BSP): apic id: %d", CPU_TO_ID(0));
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printf(", version: 0x%08x\n", cpu_apic_versions[0]);
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for (x = 1; x <= mp_naps; ++x) {
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printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x));
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printf(", version: 0x%08x\n", cpu_apic_versions[x]);
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}
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#if defined(APIC_IO)
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for (x = 0; x < mp_napics; ++x) {
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printf(" io%d (APIC): apic id: %d", x, IO_TO_ID(x));
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printf(", version: 0x%08x\n", io_apic_versions[x]);
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}
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#else
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printf(" Warning: APIC I/O disabled\n");
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#endif /* APIC_IO */
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}
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/*
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* AP cpu's call this to sync up protected mode.
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*/
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void
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init_secondary(void)
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{
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int gsel_tss, slot;
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r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1;
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r_gdt.rd_base = (int) gdt;
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lgdt(&r_gdt); /* does magic intra-segment return */
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lidt(&r_idt);
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lldt(_default_ldt);
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slot = NGDT + cpunumber();
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gsel_tss = GSEL(slot, SEL_KPL);
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gdt[slot].sd.sd_type = SDT_SYS386TSS;
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ltr(gsel_tss);
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load_cr0(0x8005003b); /* XXX! */
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}
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#if defined(APIC_IO)
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void
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configure_local_apic(void)
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{
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u_char byte;
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u_int32_t temp;
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if (picmode) {
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outb(0x22, 0x70); /* select IMCR */
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byte = inb(0x23); /* current contents */
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byte |= 0x01; /* mask external INTR */
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outb(0x23, byte); /* disconnect 8259s/NMI */
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}
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/* mask the LVT1 */
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temp = apic_base[APIC_LVT1];
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temp |= APIC_LVT_M;
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apic_base[APIC_LVT1] = temp;
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}
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#endif /* APIC_IO */
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/*******************************************************************
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* local functions and data
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*/
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static int
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mp_probe(u_int base_top)
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{
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int x;
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u_long segment;
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u_int32_t target;
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/* see if EBDA exists */
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if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) {
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/* search first 1K of EBDA */
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target = (u_int32_t) (segment << 4);
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if ((x = search_for_sig(target, 1024 / 4)) >= 0)
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goto found;
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} else {
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/*last 1K of base memory, effective 'top of base' is passed in*/
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target = (u_int32_t) (base_top - 0x400);
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if ((x = search_for_sig(target, 1024 / 4)) >= 0)
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goto found;
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}
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/* search the BIOS */
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target = (u_int32_t) BIOS_BASE;
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if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
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goto found;
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/* nothing found */
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mpfps = mpenabled = 0;
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return 0;
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found: /* please forgive the 'goto'! */
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/* flag fact that we are running multiple processors */
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mpfps = x;
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mpenabled = 1;
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return 1;
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}
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/*
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* start the SMP system
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*/
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static int parse_mp_table(void);
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static void default_mp_table(int type);
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static int start_all_aps(u_int boot_addr);
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static void
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mp_enable(u_int boot_addr)
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{
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int x;
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#if defined(APIC_IO)
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int apic;
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u_int ux;
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#endif /* APIC_IO */
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/* examine the MP table for needed info */
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x = parse_mp_table();
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/* create pages for (address common) cpu APIC and each IO APIC */
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pmap_bootstrap_apics();
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/* can't process default configs till the CPU APIC is pmapped */
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if (x)
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default_mp_table(x);
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#if defined(APIC_IO)
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/* fill the LOGICAL io_apic_versions table */
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for (apic = 0; apic < mp_napics; ++apic) {
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ux = io_apic_read(apic, IOAPIC_VER);
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io_apic_versions[apic] = ux;
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}
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/* program each IO APIC in the system */
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for (apic = 0; apic < mp_napics; ++apic)
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if (io_apic_setup(apic) < 0)
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panic("IO APIC setup failure\n");
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/* install an inter-CPU IPI for TLB invalidation */
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setidt(ICU_OFFSET + XINVLTLB_OFFSET, Xinvltlb,
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SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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#endif /* APIC_IO */
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/* start each Application Processor */
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start_all_aps(boot_addr);
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}
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/*
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* look for the MP spec signature
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*/
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/* string defined by the Intel MP Spec as identifying the MP table */
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#define MP_SIG 0x5f504d5f /* _MP_ */
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#define NEXT(X) ((X) += 4)
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static int
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search_for_sig(u_int32_t target, int count)
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{
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int x;
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u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
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for (x = 0; x < count; NEXT(x))
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if (addr[x] == MP_SIG)
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/* make array index a byte index */
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return (target + (x * sizeof(u_int32_t)));
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return -1;
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}
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#define PROCENTRY_FLAG_EN 0x01
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#define PROCENTRY_FLAG_BP 0x02
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#define IOAPICENTRY_FLAG_EN 0x01
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/* MP Floating Pointer Structure */
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typedef struct MPFPS {
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char signature[4];
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void *pap;
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u_char length;
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u_char spec_rev;
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u_char checksum;
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u_char mpfb1;
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u_char mpfb2;
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u_char mpfb3;
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u_char mpfb4;
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u_char mpfb5;
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} *mpfps_t;
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/* MP Configuration Table Header */
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typedef struct MPCTH {
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char signature[4];
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u_short base_table_length;
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u_char spec_rev;
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u_char checksum;
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u_char oem_id[8];
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u_char product_id[12];
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void *oem_table_pointer;
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u_short oem_table_size;
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u_short entry_count;
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void *apic_address;
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u_short extended_table_length;
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u_char extended_table_checksum;
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u_char reserved;
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} *mpcth_t;
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typedef struct PROCENTRY {
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u_char type;
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u_char apic_id;
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u_char apic_version;
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u_char cpu_flags;
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u_long cpu_signature;
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u_long feature_flags;
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u_long reserved1;
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u_long reserved2;
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} *proc_entry_ptr;
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typedef struct BUSENTRY {
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u_char type;
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u_char bus_id;
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char bus_type[6];
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} *bus_entry_ptr;
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typedef struct IOAPICENTRY {
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u_char type;
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u_char apic_id;
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u_char apic_version;
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u_char apic_flags;
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void *apic_address;
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} *io_apic_entry_ptr;
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typedef struct INTENTRY {
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u_char type;
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u_char int_type;
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u_short int_flags;
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u_char src_bus_id;
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u_char src_bus_irq;
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u_char dst_apic_id;
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u_char dst_apic_int;
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} *int_entry_ptr;
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/* descriptions of MP basetable entries */
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typedef struct BASETABLE_ENTRY {
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u_char type;
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u_char length;
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char name[16];
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} basetable_entry;
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static basetable_entry basetable_entry_types[] =
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{
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{0, 20, "Processor"},
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{1, 8, "Bus"},
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{2, 8, "I/O APIC"},
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{3, 8, "I/O INT"},
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{4, 8, "Local INT"}
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};
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typedef struct BUSDATA {
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u_char bus_id;
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enum busTypes bus_type;
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} bus_datum;
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typedef struct INTDATA {
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u_char int_type;
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u_short int_flags;
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u_char src_bus_id;
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u_char src_bus_irq;
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u_char dst_apic_id;
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u_char dst_apic_int;
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} io_int, local_int;
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typedef struct BUSTYPENAME {
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u_char type;
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char name[7];
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} bus_type_name;
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static bus_type_name bus_type_table[] =
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{
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{CBUS, "CBUS"},
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{CBUSII, "CBUSII"},
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{EISA, "EISA"},
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{UNKNOWN_BUSTYPE, "---"},
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{UNKNOWN_BUSTYPE, "---"},
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{ISA, "ISA"},
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{UNKNOWN_BUSTYPE, "---"},
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{UNKNOWN_BUSTYPE, "---"},
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{UNKNOWN_BUSTYPE, "---"},
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{UNKNOWN_BUSTYPE, "---"},
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{UNKNOWN_BUSTYPE, "---"},
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{UNKNOWN_BUSTYPE, "---"},
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{PCI, "PCI"},
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{UNKNOWN_BUSTYPE, "---"},
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{UNKNOWN_BUSTYPE, "---"},
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{UNKNOWN_BUSTYPE, "---"},
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{UNKNOWN_BUSTYPE, "---"},
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{XPRESS, "XPRESS"},
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{UNKNOWN_BUSTYPE, "---"}
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};
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/* from MP spec v1.4, table 5-1 */
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static int default_data[7][5] =
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{
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/* nbus, id0, type0, id1, type1 */
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{1, 0, ISA, 255, 255},
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{1, 0, EISA, 255, 255},
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{1, 0, EISA, 255, 255},
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{0, 255, 255, 255, 255},/* MCA not supported */
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{2, 0, ISA, 1, PCI},
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{2, 0, EISA, 1, PCI},
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{0, 255, 255, 255, 255} /* MCA not supported */
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};
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|
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/* the bus data */
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bus_datum bus_data[NBUS];
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|
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/* the IO INT data, one entry per possible APIC INTerrupt */
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io_int io_apic_ints[NINTR];
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static int nintrs;
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#if defined(FIX_MP_TABLE_WORKS)
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static void fix_mp_table __P((void));
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#endif /* FIX_MP_TABLE_WORKS */
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|
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static void processor_entry __P((proc_entry_ptr entry, int *cpu));
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static void io_apic_entry __P((io_apic_entry_ptr entry, int *apic));
|
|
static void bus_entry __P((bus_entry_ptr entry, int *bus));
|
|
static void int_entry __P((int_entry_ptr entry, int *intr));
|
|
static int lookup_bus_type __P((char *name));
|
|
|
|
|
|
/*
|
|
* parse an Intel MP specification table
|
|
*/
|
|
static int
|
|
parse_mp_table(void)
|
|
{
|
|
int x;
|
|
mpfps_t fps;
|
|
mpcth_t cth;
|
|
int totalSize;
|
|
void *position;
|
|
int count;
|
|
int type;
|
|
int apic, bus, cpu, intr;
|
|
|
|
/* clear physical APIC ID to logical CPU/IO table */
|
|
for (x = 0; x < NAPICID; ++x)
|
|
ID_TO_IO(x) = -1;
|
|
|
|
/* clear logical CPU to APIC ID table */
|
|
for (x = 0; x < NCPU; ++x)
|
|
CPU_TO_ID(x) = -1;
|
|
|
|
/* clear logical IO to APIC ID table */
|
|
for (x = 0; x < NAPIC; ++x)
|
|
IO_TO_ID(x) = -1;
|
|
|
|
/* clear IO APIC address table */
|
|
for (x = 0; x < NAPIC; ++x)
|
|
io_apic_address[x] = ~0;
|
|
|
|
/* clear bus data table */
|
|
for (x = 0; x < NBUS; ++x)
|
|
bus_data[x].bus_id = 0xff;
|
|
|
|
/* clear IO APIC INT table */
|
|
for (x = 0; x < NINTR; ++x)
|
|
io_apic_ints[x].int_type = 0xff;
|
|
nintrs = 0;
|
|
|
|
/* count the BSP */
|
|
mp_ncpus = 1;
|
|
|
|
/* setup the cpu/apic mapping arrays */
|
|
boot_cpu_id = -1;
|
|
|
|
/* local pointer */
|
|
fps = (mpfps_t) mpfps;
|
|
|
|
/* record whether PIC or virtual-wire mode */
|
|
picmode = (fps->mpfb2 & 0x80) ? 1 : 0;
|
|
|
|
/* check for use of 'default' configuration */
|
|
#if defined(TEST_DEFAULT_CONFIG)
|
|
/* use default addresses */
|
|
cpu_apic_address = DEFAULT_APIC_BASE;
|
|
io_apic_address[0] = DEFAULT_IO_APIC_BASE;
|
|
|
|
/* return default configuration type */
|
|
return TEST_DEFAULT_CONFIG;
|
|
#else
|
|
if (fps->mpfb1 != 0) {
|
|
/* use default addresses */
|
|
cpu_apic_address = DEFAULT_APIC_BASE;
|
|
io_apic_address[0] = DEFAULT_IO_APIC_BASE;
|
|
|
|
/* return default configuration type */
|
|
return fps->mpfb1;
|
|
}
|
|
#endif /* TEST_DEFAULT_CONFIG */
|
|
|
|
if ((cth = fps->pap) == 0)
|
|
panic("MP Configuration Table Header MISSING!\n");
|
|
|
|
cpu_apic_address = (vm_offset_t) cth->apic_address;
|
|
|
|
totalSize = cth->base_table_length - sizeof(struct MPCTH);
|
|
position = (u_char *) cth + sizeof(struct MPCTH);
|
|
count = cth->entry_count;
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|
|
|
apic = 0; /* logical apic# start @ 0 */
|
|
bus = 0; /* logical bus# start @ 0 */
|
|
cpu = 1; /* logical cpu# start @ 0, BUT reserve 0 for */
|
|
/* BSP */
|
|
intr = 0; /* unknown */
|
|
|
|
/* walk the table, recording info of interest */
|
|
while (count--) {
|
|
switch (type = *(u_char *) position) {
|
|
case 0:
|
|
processor_entry(position, &cpu);
|
|
break;
|
|
case 1:
|
|
bus_entry(position, &bus);
|
|
break;
|
|
case 2:
|
|
io_apic_entry(position, &apic);
|
|
break;
|
|
case 3:
|
|
int_entry(position, &intr);
|
|
break;
|
|
case 4:
|
|
/* int_entry(position); */
|
|
break;
|
|
default:
|
|
panic("mpfps Base Table HOSED!\n");
|
|
/* NOTREACHED */
|
|
}
|
|
|
|
totalSize -= basetable_entry_types[type].length;
|
|
(u_char *) position += basetable_entry_types[type].length;
|
|
}
|
|
|
|
if (boot_cpu_id == -1)
|
|
panic("NO BSP found!\n");
|
|
|
|
/* record # of APs found */
|
|
mp_naps = (cpu - 1);
|
|
|
|
/* record # of busses found */
|
|
mp_nbusses = bus;
|
|
|
|
/* record # of IO APICs found */
|
|
mp_napics = apic;
|
|
|
|
/* record # of IO APICs found */
|
|
nintrs = intr;
|
|
|
|
#if defined(FIX_MP_TABLE_WORKS)
|
|
/* post scan cleanup */
|
|
fix_mp_table();
|
|
#endif /* FIX_MP_TABLE_WORKS */
|
|
|
|
/* report fact that its NOT a default configuration */
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* parse an Intel MP specification table
|
|
*/
|
|
#if defined(FIX_MP_TABLE_WORKS)
|
|
static void
|
|
fix_mp_table(void)
|
|
{
|
|
int x;
|
|
int id;
|
|
int bus_0;
|
|
int bus_pci;
|
|
int num_pci_bus;
|
|
|
|
/*
|
|
* Fix mis-numbering of the PCI bus and its INT entries if the BIOS
|
|
* did it wrong. The MP spec says that when more than 1 PCI bus
|
|
* exists the BIOS must begin with bus entries for the PCI bus and use
|
|
* actual PCI bus numbering. This implies that when only 1 PCI bus
|
|
* exists the BIOS can choose to ignore this ordering, and indeed many
|
|
* MP motherboards do ignore it. This causes a problem when the PCI
|
|
* sub-system makes requests of the MP sub-system based on PCI bus
|
|
* numbers. So here we look for the situation and renumber the
|
|
* busses and associated INTs in an effort to "make it right".
|
|
*/
|
|
|
|
/* find bus 0, PCI bus, count the number of PCI busses */
|
|
for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
|
|
if (bus_data[x].bus_id == 0) {
|
|
bus_0 = x;
|
|
}
|
|
if (bus_data[x].bus_type == PCI) {
|
|
++num_pci_bus;
|
|
bus_pci = x;
|
|
}
|
|
}
|
|
/*
|
|
* bus_0 == slot of bus with ID of 0
|
|
* bus_pci == slot of last PCI bus encountered
|
|
*/
|
|
|
|
/* check the 1 PCI bus case for sanity */
|
|
if (num_pci_bus == 1) {
|
|
|
|
/* if it is number 0 all is well */
|
|
if (bus_data[bus_pci].bus_id == 0)
|
|
return;
|
|
|
|
/* mis-numbered, swap with whichever bus uses slot 0 */
|
|
|
|
/* swap the bus entry types */
|
|
bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
|
|
bus_data[bus_0].bus_type = PCI;
|
|
|
|
/* swap each relavant INTerrupt entry */
|
|
id = bus_data[bus_pci].bus_id;
|
|
for (x = 0; x < nintrs; ++x) {
|
|
if (io_apic_ints[x].src_bus_id == id) {
|
|
io_apic_ints[x].src_bus_id = 0;
|
|
}
|
|
else if (io_apic_ints[x].src_bus_id == 0) {
|
|
io_apic_ints[x].src_bus_id = id;
|
|
}
|
|
}
|
|
}
|
|
/* sanity check if more than 1 PCI bus */
|
|
else if (num_pci_bus > 1) {
|
|
for (x = 0; x < mp_nbusses; ++x) {
|
|
if (bus_data[x].bus_type != PCI)
|
|
continue;
|
|
if (bus_data[x].bus_id >= num_pci_bus ) {
|
|
printf("bad PCI bus numbering\n");
|
|
panic("\n");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif /* FIX_MP_TABLE_WORKS */
|
|
|
|
|
|
static void
|
|
processor_entry(proc_entry_ptr entry, int *cpu)
|
|
{
|
|
int x = *cpu;
|
|
|
|
/* check for usability */
|
|
if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
|
|
return;
|
|
|
|
/* check for BSP flag */
|
|
if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
|
|
/* always give boot CPU the logical value of 0 */
|
|
x = 0;
|
|
boot_cpu_id = entry->apic_id;
|
|
} else {
|
|
/* add another AP to list, if less than max number of CPUs */
|
|
if (x == NCPU) {
|
|
printf("Warning: only using %d of the available CPUs!\n", x);
|
|
return;
|
|
}
|
|
++(*cpu);
|
|
}
|
|
|
|
CPU_TO_ID(x) = entry->apic_id;
|
|
ID_TO_CPU(entry->apic_id) = x;
|
|
}
|
|
|
|
|
|
static void
|
|
bus_entry(bus_entry_ptr entry, int *bus)
|
|
{
|
|
int x, y;
|
|
char name[8];
|
|
char c;
|
|
|
|
if ((x = (*bus)++) == NBUS)
|
|
panic("too many busses, increase 'NBUS'\n");
|
|
|
|
/* encode the name into an index */
|
|
for (y = 0; y < 6; ++y) {
|
|
if ((c = entry->bus_type[y]) == ' ')
|
|
break;
|
|
name[y] = c;
|
|
}
|
|
name[y] = '\0';
|
|
|
|
if ((y = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
|
|
panic("unknown bus type: '%s'\n", name);
|
|
|
|
bus_data[x].bus_id = entry->bus_id;
|
|
bus_data[x].bus_type = y;
|
|
}
|
|
|
|
|
|
static void
|
|
io_apic_entry(io_apic_entry_ptr entry, int *apic)
|
|
{
|
|
int x;
|
|
|
|
if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
|
|
return;
|
|
|
|
if ((x = (*apic)++) == NAPIC)
|
|
panic("too many APICs, increase 'NAPIC'\n");
|
|
|
|
IO_TO_ID(x) = entry->apic_id;
|
|
ID_TO_IO(entry->apic_id) = x;
|
|
|
|
io_apic_address[x] = (vm_offset_t) entry->apic_address;
|
|
}
|
|
|
|
|
|
static int
|
|
lookup_bus_type(char *name)
|
|
{
|
|
int x;
|
|
|
|
for (x = 0; x < MAX_BUSTYPE; ++x)
|
|
if (strcmp(bus_type_table[x].name, name) == 0)
|
|
return bus_type_table[x].type;
|
|
|
|
return UNKNOWN_BUSTYPE;
|
|
}
|
|
|
|
|
|
static void
|
|
int_entry(int_entry_ptr entry, int *intr)
|
|
{
|
|
int x;
|
|
|
|
if ((x = (*intr)++) == NINTR)
|
|
panic("too many INTs, increase 'NINTR'\n");
|
|
|
|
io_apic_ints[x].int_type = entry->int_type;
|
|
io_apic_ints[x].int_flags = entry->int_flags;
|
|
io_apic_ints[x].src_bus_id = entry->src_bus_id;
|
|
io_apic_ints[x].src_bus_irq = entry->src_bus_irq;
|
|
io_apic_ints[x].dst_apic_id = entry->dst_apic_id;
|
|
io_apic_ints[x].dst_apic_int = entry->dst_apic_int;
|
|
}
|
|
|
|
|
|
static int
|
|
apic_int_is_bus_type(int intr, int bus_type)
|
|
{
|
|
int bus;
|
|
|
|
for (bus = 0; bus < mp_nbusses; ++bus)
|
|
if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
|
|
&& ((int) bus_data[bus].bus_type == bus_type))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* determine which APIC pin an ISA INT is attached to.
|
|
*/
|
|
#define INTTYPE(I) (io_apic_ints[(I)].int_type)
|
|
#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
|
|
|
|
#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
|
|
int
|
|
get_isa_apic_irq(int isaIRQ)
|
|
{
|
|
int intr;
|
|
|
|
#if defined(SMP_TIMER_NC)
|
|
if (isaIRQ == 0)
|
|
return -1;
|
|
#endif /* SMP_TIMER_NC */
|
|
|
|
for (intr = 0; intr < nintrs; ++intr) /* search each INT record */
|
|
if ((INTTYPE(intr) == 0)
|
|
&& (SRCBUSIRQ(intr) == isaIRQ)) /* a candidate IRQ */
|
|
if (apic_int_is_bus_type(intr, ISA)) /* check bus match */
|
|
return INTPIN(intr); /* exact match */
|
|
|
|
return -1; /* NOT found */
|
|
}
|
|
#undef SRCBUSIRQ
|
|
|
|
|
|
/*
|
|
*
|
|
*/
|
|
int
|
|
get_isa_apic_mask(int isaMASK)
|
|
{
|
|
int apicpin, isairq;
|
|
|
|
isairq = ffs(isaMASK);
|
|
if (isairq == 0) {
|
|
return 0;
|
|
}
|
|
|
|
apicpin = get_isa_apic_irq(isairq - 1);
|
|
if (apicpin == -1) {
|
|
return 0;
|
|
}
|
|
|
|
return (1 << apicpin);
|
|
}
|
|
|
|
|
|
/*
|
|
* determine which APIC pin an EISA INT is attached to.
|
|
*/
|
|
#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
|
|
int
|
|
get_eisa_apic_irq(int eisaIRQ)
|
|
{
|
|
int intr;
|
|
|
|
#if defined(SMP_TIMER_NC)
|
|
if (eisaIRQ == 0)
|
|
return -1;
|
|
#endif /* SMP_TIMER_NC */
|
|
|
|
for (intr = 0; intr < nintrs; ++intr) /* search each INT record */
|
|
if ((INTTYPE(intr) == 0)
|
|
&& (SRCBUSIRQ(intr) == eisaIRQ)) /* a candidate IRQ */
|
|
if (apic_int_is_bus_type(intr, EISA)) /* check bus match */
|
|
return INTPIN(intr); /* exact match */
|
|
|
|
return -1; /* NOT found */
|
|
}
|
|
#undef SRCBUSIRQ
|
|
|
|
|
|
/*
|
|
* determine which APIC pin a PCI INT is attached to.
|
|
*/
|
|
#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
|
|
#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
|
|
#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
|
|
int
|
|
get_pci_apic_irq(int pciBus, int pciDevice, int pciInt)
|
|
{
|
|
int intr;
|
|
|
|
--pciInt; /* zero based */
|
|
|
|
for (intr = 0; intr < nintrs; ++intr) /* search each record */
|
|
if ((INTTYPE(intr) == 0)
|
|
#if defined(FIX_MP_TABLE_WORKS)
|
|
&& (SRCBUSID(intr) == pciBus)
|
|
#endif /* FIX_MP_TABLE_WORKS */
|
|
&& (SRCBUSDEVICE(intr) == pciDevice)
|
|
&& (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
|
|
if (apic_int_is_bus_type(intr, PCI)) /* check bus match */
|
|
return INTPIN(intr); /* exact match */
|
|
|
|
return -1; /* NOT found */
|
|
}
|
|
#undef SRCBUSLINE
|
|
#undef SRCBUSDEVICE
|
|
#undef SRCBUSID
|
|
|
|
#undef INTPIN
|
|
#undef INTTYPE
|
|
|
|
|
|
int
|
|
undirect_pci_irq(int rirq)
|
|
{
|
|
#if defined(READY)
|
|
printf("Freeing irq %d for ISA cards.\n", rirq);
|
|
/** FIXME: tickle the MB redirector chip */
|
|
return ???;
|
|
#else
|
|
printf("Freeing (NOT implemented) irq %d for ISA cards.\n", rirq);
|
|
return 0;
|
|
#endif /* READY */
|
|
}
|
|
|
|
|
|
/*
|
|
* given a bus ID, return:
|
|
* the bus type if found
|
|
* -1 if NOT found
|
|
*/
|
|
int
|
|
apic_bus_type(int id)
|
|
{
|
|
int x;
|
|
|
|
for (x = 0; x < mp_nbusses; ++x)
|
|
if (bus_data[x].bus_id == id)
|
|
return bus_data[x].bus_type;
|
|
|
|
return -1;
|
|
}
|
|
|
|
|
|
/*
|
|
* given a LOGICAL APIC# and pin#, return:
|
|
* the associated src bus ID if found
|
|
* -1 if NOT found
|
|
*/
|
|
int
|
|
apic_src_bus_id(int apic, int pin)
|
|
{
|
|
int x;
|
|
|
|
/* search each of the possible INTerrupt sources */
|
|
for (x = 0; x < nintrs; ++x)
|
|
if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
|
|
(pin == io_apic_ints[x].dst_apic_int))
|
|
return (io_apic_ints[x].src_bus_id);
|
|
|
|
return -1; /* NOT found */
|
|
}
|
|
|
|
|
|
/*
|
|
* given a LOGICAL APIC# and pin#, return:
|
|
* the associated src bus IRQ if found
|
|
* -1 if NOT found
|
|
*/
|
|
int
|
|
apic_src_bus_irq(int apic, int pin)
|
|
{
|
|
int x;
|
|
|
|
for (x = 0; x < nintrs; x++)
|
|
if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
|
|
(pin == io_apic_ints[x].dst_apic_int))
|
|
return (io_apic_ints[x].src_bus_irq);
|
|
|
|
return -1; /* NOT found */
|
|
}
|
|
|
|
|
|
/*
|
|
* given a LOGICAL APIC# and pin#, return:
|
|
* the associated INTerrupt type if found
|
|
* -1 if NOT found
|
|
*/
|
|
int
|
|
apic_int_type(int apic, int pin)
|
|
{
|
|
int x;
|
|
|
|
/* search each of the possible INTerrupt sources */
|
|
for (x = 0; x < nintrs; ++x)
|
|
if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
|
|
(pin == io_apic_ints[x].dst_apic_int))
|
|
return (io_apic_ints[x].int_type);
|
|
|
|
return -1; /* NOT found */
|
|
}
|
|
|
|
|
|
/*
|
|
* given a LOGICAL APIC# and pin#, return:
|
|
* the associated trigger mode if found
|
|
* -1 if NOT found
|
|
*/
|
|
int
|
|
apic_trigger(int apic, int pin)
|
|
{
|
|
int x;
|
|
|
|
/* search each of the possible INTerrupt sources */
|
|
for (x = 0; x < nintrs; ++x)
|
|
if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
|
|
(pin == io_apic_ints[x].dst_apic_int))
|
|
return ((io_apic_ints[x].int_flags >> 2) & 0x03);
|
|
|
|
return -1; /* NOT found */
|
|
}
|
|
|
|
|
|
/*
|
|
* given a LOGICAL APIC# and pin#, return:
|
|
* the associated 'active' level if found
|
|
* -1 if NOT found
|
|
*/
|
|
int
|
|
apic_polarity(int apic, int pin)
|
|
{
|
|
int x;
|
|
|
|
/* search each of the possible INTerrupt sources */
|
|
for (x = 0; x < nintrs; ++x)
|
|
if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
|
|
(pin == io_apic_ints[x].dst_apic_int))
|
|
return (io_apic_ints[x].int_flags & 0x03);
|
|
|
|
return -1; /* NOT found */
|
|
}
|
|
|
|
|
|
/*
|
|
* set data according to MP defaults
|
|
* FIXME: probably not complete yet...
|
|
*/
|
|
static void
|
|
default_mp_table(int type)
|
|
{
|
|
int ap_cpu_id;
|
|
#if defined(APIC_IO)
|
|
u_int32_t ux;
|
|
int io_apic_id;
|
|
int pin;
|
|
#endif /* APIC_IO */
|
|
|
|
#if 0
|
|
printf(" MP default config type: %d\n", type);
|
|
switch (type) {
|
|
case 1:
|
|
printf(" bus: ISA, APIC: 82489DX\n");
|
|
break;
|
|
case 2:
|
|
printf(" bus: EISA, APIC: 82489DX\n");
|
|
break;
|
|
case 3:
|
|
printf(" bus: EISA, APIC: 82489DX\n");
|
|
break;
|
|
case 4:
|
|
printf(" bus: MCA, APIC: 82489DX\n");
|
|
break;
|
|
case 5:
|
|
printf(" bus: ISA+PCI, APIC: Integrated\n");
|
|
break;
|
|
case 6:
|
|
printf(" bus: EISA+PCI, APIC: Integrated\n");
|
|
break;
|
|
case 7:
|
|
printf(" bus: MCA+PCI, APIC: Integrated\n");
|
|
break;
|
|
default:
|
|
printf(" future type\n");
|
|
break;
|
|
/* NOTREACHED */
|
|
}
|
|
#endif /* 0 */
|
|
|
|
boot_cpu_id = (apic_base[APIC_ID] & APIC_ID_MASK) >> 24;
|
|
ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
|
|
|
|
/* BSP */
|
|
CPU_TO_ID(0) = boot_cpu_id;
|
|
ID_TO_CPU(boot_cpu_id) = 0;
|
|
|
|
/* one and only AP */
|
|
CPU_TO_ID(1) = ap_cpu_id;
|
|
ID_TO_CPU(ap_cpu_id) = 1;
|
|
mp_naps = 1;
|
|
|
|
/* one and only IO APIC */
|
|
#if defined(APIC_IO)
|
|
io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
|
|
|
|
/*
|
|
* sanity check, refer to MP spec section 3.6.6, last paragraph
|
|
* necessary as some hardware isn't properly setting up the IO APIC
|
|
*/
|
|
#if defined(REALLY_ANAL_IOAPICID_VALUE)
|
|
if (io_apic_id != 2) {
|
|
#else
|
|
if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
|
|
#endif /* REALLY_ANAL_IOAPICID_VALUE */
|
|
ux = io_apic_read(0, IOAPIC_ID); /* get current contents */
|
|
ux &= ~APIC_ID_MASK; /* clear the ID field */
|
|
ux |= 0x02000000; /* set it to '2' */
|
|
io_apic_write(0, IOAPIC_ID, ux); /* write new value */
|
|
ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */
|
|
if ((ux & APIC_ID_MASK) != 0x02000000)
|
|
panic("Problem: can't control IO APIC ID, reg: 0x%08x\n", ux);
|
|
io_apic_id = 2;
|
|
}
|
|
IO_TO_ID(0) = io_apic_id;
|
|
ID_TO_IO(io_apic_id) = 0;
|
|
mp_napics = 1;
|
|
#else
|
|
mp_napics = 0;
|
|
#endif /* APIC_IO */
|
|
|
|
/* fill out bus entries */
|
|
switch (type) {
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
case 5:
|
|
case 6:
|
|
mp_nbusses = default_data[type - 1][0];
|
|
bus_data[0].bus_id = default_data[type - 1][1];
|
|
bus_data[0].bus_type = default_data[type - 1][2];
|
|
bus_data[1].bus_id = default_data[type - 1][3];
|
|
bus_data[1].bus_type = default_data[type - 1][4];
|
|
break;
|
|
|
|
/* case 4: case 7: MCA NOT supported */
|
|
default: /* illegal/reserved */
|
|
panic("BAD default MP config: %d\n", type);
|
|
}
|
|
|
|
#if defined(APIC_IO)
|
|
/* general cases from MP v1.4, table 5-2 */
|
|
for (pin = 0; pin < 16; ++pin) {
|
|
io_apic_ints[pin].int_type = 0;
|
|
io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */
|
|
io_apic_ints[pin].src_bus_id = 0;
|
|
io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */
|
|
io_apic_ints[pin].dst_apic_id = io_apic_id;
|
|
io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */
|
|
}
|
|
|
|
/* special cases from MP v1.4, table 5-2 */
|
|
if (type == 2) {
|
|
io_apic_ints[2].int_type = 0xff; /* N/C */
|
|
io_apic_ints[13].int_type = 0xff; /* N/C */
|
|
#if !defined(APIC_MIXED_MODE)
|
|
/** FIXME: ??? */
|
|
panic("sorry, can't support type 2 default yet\n");
|
|
#endif /* APIC_MIXED_MODE */
|
|
} else
|
|
io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
|
|
|
|
if (type == 7)
|
|
io_apic_ints[0].int_type = 0xff; /* N/C */
|
|
else
|
|
io_apic_ints[0].int_type = 3; /* vectored 8259 */
|
|
|
|
nintrs = 16;
|
|
#endif /* APIC_IO */
|
|
}
|
|
|
|
|
|
static void install_ap_tramp(u_int boot_addr);
|
|
static int start_ap(int logicalCpu, u_int boot_addr);
|
|
|
|
/*
|
|
* start each AP in our list
|
|
*/
|
|
static int
|
|
start_all_aps(u_int boot_addr)
|
|
{
|
|
int x;
|
|
u_char mpbiosreason;
|
|
u_long mpbioswarmvec;
|
|
|
|
/**
|
|
* NOTE: this needs further thought:
|
|
* where does it get released?
|
|
* should it be set to empy?
|
|
*
|
|
* get the initial mp_lock with a count of 1 for the BSP
|
|
*/
|
|
mp_lock = (apic_base[APIC_ID] & APIC_ID_MASK) + 1;
|
|
|
|
/* initialize BSP's local APIC */
|
|
apic_initialize(1);
|
|
|
|
/* install the AP 1st level boot code */
|
|
install_ap_tramp(boot_addr);
|
|
|
|
/* save the current value of the warm-start vector */
|
|
mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
|
|
outb(CMOS_REG, BIOS_RESET);
|
|
mpbiosreason = inb(CMOS_DATA);
|
|
|
|
/* start each AP */
|
|
for (x = 1; x <= mp_naps; ++x) {
|
|
|
|
/* setup a vector to our boot code */
|
|
*((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
|
|
*((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
|
|
outb(CMOS_REG, BIOS_RESET);
|
|
outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
|
|
|
|
/* attempt to start the Application Processor */
|
|
CHECK_INIT(99); /* setup checkpoints */
|
|
if (!start_ap(x, boot_addr)) {
|
|
printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
|
|
CHECK_PRINT("trace"); /* show checkpoints */
|
|
/*
|
|
* better panic as the AP may be running loose
|
|
* somewhere
|
|
*/
|
|
printf("panic y/n? [n] ");
|
|
if (cngetc() != 'n')
|
|
panic("bye-bye\n");
|
|
}
|
|
CHECK_PRINT("trace"); /* show checkpoints */
|
|
|
|
/* record its version info */
|
|
cpu_apic_versions[x] = cpu_apic_versions[0];
|
|
}
|
|
|
|
/* fill in our (BSP) APIC version */
|
|
cpu_apic_versions[0] = apic_base[APIC_VER];
|
|
|
|
/* restore the warmstart vector */
|
|
*(u_long *) WARMBOOT_OFF = mpbioswarmvec;
|
|
outb(CMOS_REG, BIOS_RESET);
|
|
outb(CMOS_DATA, mpbiosreason);
|
|
|
|
/* number of APs actually started */
|
|
return mp_ncpus - 1;
|
|
}
|
|
|
|
|
|
/*
|
|
* load the 1st level AP boot code into base memory.
|
|
*/
|
|
|
|
/* targets for relocation */
|
|
extern void bigJump(void);
|
|
extern void bootCodeSeg(void);
|
|
extern void bootDataSeg(void);
|
|
extern void MPentry(void);
|
|
extern u_int MP_GDT;
|
|
extern u_int mp_gdtbase;
|
|
|
|
static void
|
|
install_ap_tramp(u_int boot_addr)
|
|
{
|
|
int x;
|
|
int size = *(int *) ((u_long) & bootMP_size);
|
|
u_char *src = (u_char *) ((u_long) bootMP);
|
|
u_char *dst = (u_char *) boot_addr + KERNBASE;
|
|
u_int boot_base = (u_int) bootMP;
|
|
u_int8_t *dst8;
|
|
u_int16_t *dst16;
|
|
u_int32_t *dst32;
|
|
|
|
for (x = 0; x < size; ++x)
|
|
*dst++ = *src++;
|
|
|
|
/*
|
|
* modify addresses in code we just moved to basemem. unfortunately we
|
|
* need fairly detailed info about mpboot.s for this to work. changes
|
|
* to mpboot.s might require changes here.
|
|
*/
|
|
|
|
/* boot code is located in KERNEL space */
|
|
dst = (u_char *) boot_addr + KERNBASE;
|
|
|
|
/* modify the lgdt arg */
|
|
dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
|
|
*dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
|
|
|
|
/* modify the ljmp target for MPentry() */
|
|
dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
|
|
*dst32 = ((u_int) MPentry - KERNBASE);
|
|
|
|
/* modify the target for boot code segment */
|
|
dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
|
|
dst8 = (u_int8_t *) (dst16 + 1);
|
|
*dst16 = (u_int) boot_addr & 0xffff;
|
|
*dst8 = ((u_int) boot_addr >> 16) & 0xff;
|
|
|
|
/* modify the target for boot data segment */
|
|
dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
|
|
dst8 = (u_int8_t *) (dst16 + 1);
|
|
*dst16 = (u_int) boot_addr & 0xffff;
|
|
*dst8 = ((u_int) boot_addr >> 16) & 0xff;
|
|
}
|
|
|
|
|
|
/*
|
|
* this function starts the AP (application processor) identified
|
|
* by the APIC ID 'physicalCpu'. It does quite a "song and dance"
|
|
* to accomplish this. This is necessary because of the nuances
|
|
* of the different hardware we might encounter. It ain't pretty,
|
|
* but it seems to work.
|
|
*/
|
|
static int
|
|
start_ap(int logical_cpu, u_int boot_addr)
|
|
{
|
|
int physical_cpu;
|
|
int vector;
|
|
int cpus;
|
|
u_long icr_lo, icr_hi;
|
|
|
|
/* get the PHYSICAL APIC ID# */
|
|
physical_cpu = CPU_TO_ID(logical_cpu);
|
|
|
|
/* calculate the vector */
|
|
vector = (boot_addr >> 12) & 0xff;
|
|
|
|
/* used as a watchpoint to signal AP startup */
|
|
cpus = mp_ncpus;
|
|
|
|
/*
|
|
* first we do an INIT/RESET IPI this INIT IPI might be run, reseting
|
|
* and running the target CPU. OR this INIT IPI might be latched (P5
|
|
* bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
|
|
* ignored.
|
|
*/
|
|
|
|
/* setup the address for the target AP */
|
|
icr_hi = apic_base[APIC_ICR_HI] & ~APIC_ID_MASK;
|
|
icr_hi |= (physical_cpu << 24);
|
|
apic_base[APIC_ICR_HI] = icr_hi;
|
|
|
|
/* do an INIT IPI: assert RESET */
|
|
icr_lo = apic_base[APIC_ICR_LOW] & 0xfff00000;
|
|
apic_base[APIC_ICR_LOW] = icr_lo | 0x0000c500;
|
|
|
|
/* wait for pending status end */
|
|
while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK)
|
|
/* spin */ ;
|
|
|
|
/* do an INIT IPI: deassert RESET */
|
|
apic_base[APIC_ICR_LOW] = icr_lo | 0x00008500;
|
|
|
|
/* wait for pending status end */
|
|
u_sleep(10000); /* wait ~10mS */
|
|
while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK)
|
|
/* spin */ ;
|
|
|
|
/*
|
|
* next we do a STARTUP IPI: the previous INIT IPI might still be
|
|
* latched, (P5 bug) this 1st STARTUP would then terminate
|
|
* immediately, and the previously started INIT IPI would continue. OR
|
|
* the previous INIT IPI has already run. and this STARTUP IPI will
|
|
* run. OR the previous INIT IPI was ignored. and this STARTUP IPI
|
|
* will run.
|
|
*/
|
|
|
|
/* do a STARTUP IPI */
|
|
apic_base[APIC_ICR_LOW] = icr_lo | 0x00000600 | vector;
|
|
while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK)
|
|
/* spin */ ;
|
|
u_sleep(200); /* wait ~200uS */
|
|
|
|
/*
|
|
* finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
|
|
* the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
|
|
* this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
|
|
* recognized after hardware RESET or INIT IPI.
|
|
*/
|
|
|
|
apic_base[APIC_ICR_LOW] = icr_lo | 0x00000600 | vector;
|
|
while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK)
|
|
/* spin */ ;
|
|
u_sleep(200); /* wait ~200uS */
|
|
|
|
/* wait for it to start */
|
|
set_apic_timer(5000000);/* == 5 seconds */
|
|
while (read_apic_timer())
|
|
if (mp_ncpus > cpus)
|
|
return 1; /* return SUCCESS */
|
|
|
|
return 0; /* return FAILURE */
|
|
}
|
|
|
|
|
|
/*
|
|
* Flush the TLB on all other CPU's
|
|
*
|
|
* XXX: Needs to handshake and wait for completion before proceding.
|
|
*/
|
|
void
|
|
smp_invltlb(void)
|
|
{
|
|
#if defined(APIC_IO)
|
|
if (smp_active && invltlb_ok)
|
|
all_but_self_ipi(ICU_OFFSET + XINVLTLB_OFFSET);
|
|
#endif /* APIC_IO */
|
|
}
|
|
|
|
void
|
|
invlpg(u_int addr)
|
|
{
|
|
__asm __volatile("invlpg (%0)"::"r"(addr):"memory");
|
|
|
|
/* send a message to the other CPUs */
|
|
smp_invltlb();
|
|
}
|
|
|
|
void
|
|
invltlb(void)
|
|
{
|
|
u_long temp;
|
|
|
|
/*
|
|
* This should be implemented as load_cr3(rcr3()) when load_cr3() is
|
|
* inlined.
|
|
*/
|
|
__asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory");
|
|
|
|
/* send a message to the other CPUs */
|
|
smp_invltlb();
|
|
}
|