Rafal Jaworowski c72ef339bf Adjust mvs(4) to handle interrupt cause reg depending on the actual number of ... channels available - current code treats bits 4:7 in 'SATAHC interrupt mask' and 'SATAHC interrupt cause' as flags for SATA channels 2 and 3 - for embedded SATA controllers (SoC) these bits have been marked as reserved in datasheets so far, but for some new and upcoming chips they are used for purposes other than SATA Submitted by: Lukasz Plachno Reviewed by: mav Obtained from: Semihalf MFC after: 2 weeks		2012-02-01 13:39:52 +00:00
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mvs_if.m
mvs_pci.c
mvs_soc.c	Adjust mvs(4) to handle interrupt cause reg depending on the actual number of	2012-02-01 13:39:52 +00:00
mvs.c
mvs.h	Adjust mvs(4) to handle interrupt cause reg depending on the actual number of	2012-02-01 13:39:52 +00:00