392 lines
9.9 KiB
C
392 lines
9.9 KiB
C
/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */
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/*-
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* Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
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* Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
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* Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_wlan.h"
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#include <sys/param.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/mbuf.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/taskqueue.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/linker.h>
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#include <net/if.h>
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#include <net/ethernet.h>
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#include <net/if_media.h>
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#include <net80211/ieee80211_var.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/rtwn/if_rtwnreg.h>
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#include <dev/rtwn/if_rtwnvar.h>
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#include <dev/rtwn/if_rtwn_debug.h>
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#include <dev/rtwn/usb/rtwn_usb_var.h>
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#include <dev/rtwn/rtl8192c/r92c_var.h>
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#include <dev/rtwn/rtl8192c/usb/r92cu.h>
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#include <dev/rtwn/rtl8192c/usb/r92cu_reg.h>
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void
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r92cu_init_bb(struct rtwn_softc *sc)
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{
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/* Enable BB and RF. */
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rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
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R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
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R92C_SYS_FUNC_EN_DIO_RF);
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rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
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rtwn_write_1(sc, R92C_RF_CTRL,
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R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
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rtwn_write_1(sc, R92C_SYS_FUNC_EN,
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R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
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R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
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rtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f);
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rtwn_write_1(sc, 0x15, 0xe9);
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rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
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r92c_init_bb_common(sc);
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}
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int
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r92cu_power_on(struct rtwn_softc *sc)
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{
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#define RTWN_CHK(res) do { \
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if (res != 0) \
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return (EIO); \
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} while(0)
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uint32_t reg;
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int ntries;
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/* Wait for autoload done bit. */
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for (ntries = 0; ntries < 5000; ntries++) {
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if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000) {
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device_printf(sc->sc_dev,
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"timeout waiting for chip autoload\n");
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return (ETIMEDOUT);
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}
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/* Unlock ISO/CLK/Power control register. */
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RTWN_CHK(rtwn_write_1(sc, R92C_RSV_CTRL, 0));
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/* Move SPS into PWM mode. */
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RTWN_CHK(rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b));
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/* just in case if power_off() was not properly executed. */
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rtwn_delay(sc, 100);
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reg = rtwn_read_1(sc, R92C_LDOV12D_CTRL);
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if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {
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RTWN_CHK(rtwn_write_1(sc, R92C_LDOV12D_CTRL,
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reg | R92C_LDOV12D_CTRL_LDV12_EN));
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rtwn_delay(sc, 100);
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RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_ISO_CTRL,
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R92C_SYS_ISO_CTRL_MD2PP, 0));
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}
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/* Auto enable WLAN. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
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R92C_APS_FSMCO_APFM_ONMAC, 1));
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for (ntries = 0; ntries < 5000; ntries++) {
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if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
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R92C_APS_FSMCO_APFM_ONMAC))
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000) {
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device_printf(sc->sc_dev,
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"timeout waiting for MAC auto ON\n");
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return (ETIMEDOUT);
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}
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/* Enable radio, GPIO and LED functions. */
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RTWN_CHK(rtwn_write_2(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_AFSM_HSUS |
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R92C_APS_FSMCO_PDN_EN |
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R92C_APS_FSMCO_PFM_ALDN));
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/* Release RF digital isolation. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_SYS_ISO_CTRL,
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R92C_SYS_ISO_CTRL_DIOR, 0, 1));
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/* Initialize MAC. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_APSD_CTRL,
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R92C_APSD_CTRL_OFF, 0));
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for (ntries = 0; ntries < 1000; ntries++) {
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if (!(rtwn_read_1(sc, R92C_APSD_CTRL) &
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R92C_APSD_CTRL_OFF_STATUS))
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break;
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rtwn_delay(sc, 50);
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}
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if (ntries == 1000) {
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device_printf(sc->sc_dev,
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"timeout waiting for MAC initialization\n");
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return (ETIMEDOUT);
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}
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/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
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RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
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R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
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R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
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R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
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((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
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R92C_CR_CALTMR_EN));
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RTWN_CHK(rtwn_write_1(sc, 0xfe10, 0x19));
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return (0);
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#undef RTWN_CHK
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}
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void
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r92cu_power_off(struct rtwn_softc *sc)
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{
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#ifndef RTWN_WITHOUT_UCODE
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struct r92c_softc *rs = sc->sc_priv;
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#endif
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uint32_t reg;
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int error;
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/* Deinit C2H event handler. */
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#ifndef RTWN_WITHOUT_UCODE
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callout_stop(&rs->rs_c2h_report);
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rs->rs_c2h_paused = 0;
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rs->rs_c2h_pending = 0;
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rs->rs_c2h_timeout = hz;
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#endif
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/* Block all Tx queues. */
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error = rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
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if (error == ENXIO) /* hardware gone */
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return;
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/* Disable RF */
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rtwn_rf_write(sc, 0, 0, 0);
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rtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF);
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/* Reset BB state machine */
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rtwn_write_1(sc, R92C_SYS_FUNC_EN,
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R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA |
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R92C_SYS_FUNC_EN_BB_GLB_RST);
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rtwn_write_1(sc, R92C_SYS_FUNC_EN,
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R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA);
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/*
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* Reset digital sequence
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*/
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#ifndef RTWN_WITHOUT_UCODE
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if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) {
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/* Reset MCU ready status */
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rtwn_write_1(sc, R92C_MCUFWDL, 0);
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/* If firmware in ram code, do reset */
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r92c_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
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}
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#endif
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/* Reset MAC and Enable 8051 */
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rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1,
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(R92C_SYS_FUNC_EN_CPUEN |
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R92C_SYS_FUNC_EN_ELDR |
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R92C_SYS_FUNC_EN_HWPDN) >> 8);
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/* Reset MCU ready status */
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rtwn_write_1(sc, R92C_MCUFWDL, 0);
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/* Disable MAC clock */
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rtwn_write_2(sc, R92C_SYS_CLKR,
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R92C_SYS_CLKR_ANAD16V_EN |
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R92C_SYS_CLKR_ANA8M |
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R92C_SYS_CLKR_LOADER_EN |
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R92C_SYS_CLKR_80M_SSC_DIS |
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R92C_SYS_CLKR_SYS_EN |
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R92C_SYS_CLKR_RING_EN |
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0x4000);
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/* Disable AFE PLL */
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rtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80);
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/* Gated AFE DIG_CLOCK */
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rtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F);
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/* Isolated digital to PON */
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rtwn_write_1(sc, R92C_SYS_ISO_CTRL,
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R92C_SYS_ISO_CTRL_MD2PP |
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R92C_SYS_ISO_CTRL_PA2PCIE |
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R92C_SYS_ISO_CTRL_PD2CORE |
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R92C_SYS_ISO_CTRL_IP2MAC |
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R92C_SYS_ISO_CTRL_DIOP |
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R92C_SYS_ISO_CTRL_DIOE);
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/*
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* Pull GPIO PIN to balance level and LED control
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*/
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/* 1. Disable GPIO[7:0] */
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rtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000);
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reg = rtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00;
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reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000;
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rtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg);
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/* Disable GPIO[10:8] */
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rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x00);
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reg = rtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0;
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reg |= (((reg & 0x000f) << 4) | 0x0780);
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rtwn_write_2(sc, R92C_GPIO_IO_SEL, reg);
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/* Disable LED0 & 1 */
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rtwn_write_2(sc, R92C_LEDCFG0, 0x8080);
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/*
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* Reset digital sequence
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*/
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/* Disable ELDR clock */
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rtwn_write_2(sc, R92C_SYS_CLKR,
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R92C_SYS_CLKR_ANAD16V_EN |
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R92C_SYS_CLKR_ANA8M |
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R92C_SYS_CLKR_LOADER_EN |
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R92C_SYS_CLKR_80M_SSC_DIS |
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R92C_SYS_CLKR_SYS_EN |
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R92C_SYS_CLKR_RING_EN |
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0x4000);
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/* Isolated ELDR to PON */
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rtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1,
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(R92C_SYS_ISO_CTRL_DIOR |
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R92C_SYS_ISO_CTRL_PWC_EV12V) >> 8);
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/*
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* Disable analog sequence
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*/
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/* Disable A15 power */
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rtwn_write_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_OBUF);
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/* Disable digital core power */
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rtwn_setbits_1(sc, R92C_LDOV12D_CTRL,
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R92C_LDOV12D_CTRL_LDV12_EN, 0);
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/* Enter PFM mode */
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rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23);
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/* Set USB suspend */
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rtwn_write_2(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_APDM_HOST |
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R92C_APS_FSMCO_AFSM_HSUS |
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R92C_APS_FSMCO_PFM_ALDN);
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/* Lock ISO/CLK/Power control register. */
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rtwn_write_1(sc, R92C_RSV_CTRL, 0x0E);
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}
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void
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r92cu_init_intr(struct rtwn_softc *sc)
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{
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rtwn_write_4(sc, R92C_HISR, 0xffffffff);
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rtwn_write_4(sc, R92C_HIMR, 0xffffffff);
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}
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void
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r92cu_init_tx_agg(struct rtwn_softc *sc)
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{
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struct rtwn_usb_softc *uc = RTWN_USB_SOFTC(sc);
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uint32_t reg;
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reg = rtwn_read_4(sc, R92C_TDECTRL);
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reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, uc->tx_agg_desc_num);
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rtwn_write_4(sc, R92C_TDECTRL, reg);
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}
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void
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r92cu_init_rx_agg(struct rtwn_softc *sc)
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{
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/* Rx aggregation (DMA & USB). */
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rtwn_setbits_1(sc, R92C_TRXDMA_CTRL, 0,
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R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
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rtwn_setbits_1(sc, R92C_USB_SPECIAL_OPTION, 0,
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R92C_USB_SPECIAL_OPTION_AGG_EN);
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/* XXX dehardcode */
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rtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
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rtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4);
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rtwn_write_1(sc, R92C_USB_AGG_TH, 8);
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rtwn_write_1(sc, R92C_USB_AGG_TO, 6);
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}
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void
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r92cu_post_init(struct rtwn_softc *sc)
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{
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/* Perform LO and IQ calibrations. */
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r92c_iq_calib(sc);
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/* Perform LC calibration. */
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r92c_lc_calib(sc);
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/* Fix USB interference issue. */
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rtwn_write_1(sc, 0xfe40, 0xe0);
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rtwn_write_1(sc, 0xfe41, 0x8d);
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rtwn_write_1(sc, 0xfe42, 0x80);
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r92c_pa_bias_init(sc);
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/* Fix for lower temperature. */
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rtwn_write_1(sc, 0x15, 0xe9);
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#ifndef RTWN_WITHOUT_UCODE
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if (sc->sc_flags & RTWN_FW_LOADED) {
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struct r92c_softc *rs = sc->sc_priv;
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if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) {
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/* XXX firmware RA does not work yet */
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sc->sc_ratectl = RTWN_RATECTL_NET80211;
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} else
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sc->sc_ratectl = sc->sc_ratectl_sysctl;
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/* Start C2H event handling. */
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callout_reset(&rs->rs_c2h_report, rs->rs_c2h_timeout,
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r92c_handle_c2h_report, sc);
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} else
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#endif
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sc->sc_ratectl = RTWN_RATECTL_NONE;
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}
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