517904de5c
This controller supports 2.5G/1G/100MB/10MB speeds, and allows
tx/rx checksum offload, TSO, LRO, and multi-queue operation.
The driver was derived from code contributed by Intel, and modified
by Netgate to fit into the iflib framework.
Thanks to Mike Karels for testing and feedback on the driver.
Reviewed by: bcr (manpages), kbowling, scottl, erj
MFC after: 1 month
Relnotes: yes
Sponsored by: Rubicon Communications, LLC ("Netgate")
Differential Revision: https://reviews.freebsd.org/D30668
132 lines
4.5 KiB
C
132 lines
4.5 KiB
C
/*-
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* Copyright 2021 Intel Corp
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* Copyright 2021 Rubicon Communications, LLC (Netgate)
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* $FreeBSD$
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*/
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#ifndef _IGC_BASE_H_
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#define _IGC_BASE_H_
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/* forward declaration */
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s32 igc_init_hw_base(struct igc_hw *hw);
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void igc_power_down_phy_copper_base(struct igc_hw *hw);
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extern void igc_rx_fifo_flush_base(struct igc_hw *hw);
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s32 igc_acquire_phy_base(struct igc_hw *hw);
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void igc_release_phy_base(struct igc_hw *hw);
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/* Transmit Descriptor - Advanced */
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union igc_adv_tx_desc {
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struct {
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__le64 buffer_addr; /* Address of descriptor's data buf */
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__le32 cmd_type_len;
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__le32 olinfo_status;
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} read;
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struct {
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__le64 rsvd; /* Reserved */
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__le32 nxtseq_seed;
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__le32 status;
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} wb;
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};
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/* Context descriptors */
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struct igc_adv_tx_context_desc {
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__le32 vlan_macip_lens;
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union {
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__le32 launch_time;
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__le32 seqnum_seed;
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};
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__le32 type_tucmd_mlhl;
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__le32 mss_l4len_idx;
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};
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/* Adv Transmit Descriptor Config Masks */
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#define IGC_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
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#define IGC_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
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#define IGC_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
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#define IGC_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
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#define IGC_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
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#define IGC_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
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#define IGC_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
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#define IGC_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
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#define IGC_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
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#define IGC_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */
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#define IGC_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */
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#define IGC_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */
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#define IGC_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
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#define IGC_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
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#define IGC_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
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#define IGC_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
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/* 1st & Last TSO-full iSCSI PDU*/
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#define IGC_ADVTXD_POPTS_ISCO_FULL 0x00001800
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#define IGC_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
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#define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
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/* Advanced Transmit Context Descriptor Config */
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#define IGC_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
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#define IGC_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
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#define IGC_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
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#define IGC_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
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#define IGC_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
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#define IGC_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
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#define IGC_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
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#define IGC_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
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/* IPSec Encrypt Enable for ESP */
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#define IGC_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000
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/* Req requires Markers and CRC */
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#define IGC_ADVTXD_TUCMD_MKRREQ 0x00002000
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#define IGC_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
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#define IGC_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
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/* Adv ctxt IPSec SA IDX mask */
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#define IGC_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF
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/* Adv ctxt IPSec ESP len mask */
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#define IGC_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF
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#define IGC_RAR_ENTRIES_BASE 16
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/* Receive Descriptor - Advanced */
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union igc_adv_rx_desc {
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struct {
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__le64 pkt_addr; /* Packet buffer address */
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__le64 hdr_addr; /* Header buffer address */
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} read;
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struct {
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struct {
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union {
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__le32 data;
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struct {
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__le16 pkt_info; /*RSS type, Pkt type*/
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/* Split Header, header buffer len */
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__le16 hdr_info;
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} hs_rss;
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} lo_dword;
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union {
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__le32 rss; /* RSS Hash */
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struct {
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__le16 ip_id; /* IP id */
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__le16 csum; /* Packet Checksum */
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} csum_ip;
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} hi_dword;
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} lower;
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struct {
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__le32 status_error; /* ext status/error */
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__le16 length; /* Packet length */
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__le16 vlan; /* VLAN tag */
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} upper;
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} wb; /* writeback */
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};
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/* Additional Transmit Descriptor Control definitions */
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#define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
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/* Additional Receive Descriptor Control definitions */
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#define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */
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/* SRRCTL bit definitions */
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#define IGC_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
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#define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
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#define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
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#endif /* _IGC_BASE_H_ */
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