8bd3845d3c
tunables to modify the default cpu topology advertised by bhyve. Also add a tunable "hw.vmm.topology.cpuid_leaf_b" to disable the CPUID leaf 0xb. This is intended for testing guest behavior when it falls back on using CPUID leaf 0x4 to deduce CPU topology. The default behavior is to advertise each vcpu as a core in a separate soket.
422 lines
10 KiB
C
422 lines
10 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/pcpu.h>
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#include <sys/systm.h>
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#include <sys/cpuset.h>
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#include <sys/sysctl.h>
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#include <machine/clock.h>
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#include <machine/cpufunc.h>
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#include <machine/md_var.h>
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#include <machine/segments.h>
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#include <machine/specialreg.h>
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#include <machine/vmm.h>
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#include "vmm_host.h"
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#include "x86.h"
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SYSCTL_DECL(_hw_vmm);
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static SYSCTL_NODE(_hw_vmm, OID_AUTO, topology, CTLFLAG_RD, 0, NULL);
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#define CPUID_VM_HIGH 0x40000000
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static const char bhyve_id[12] = "bhyve bhyve ";
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static uint64_t bhyve_xcpuids;
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/*
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* The default CPU topology is a single thread per package.
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*/
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static u_int threads_per_core = 1;
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SYSCTL_UINT(_hw_vmm_topology, OID_AUTO, threads_per_core, CTLFLAG_RDTUN,
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&threads_per_core, 0, NULL);
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static u_int cores_per_package = 1;
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SYSCTL_UINT(_hw_vmm_topology, OID_AUTO, cores_per_package, CTLFLAG_RDTUN,
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&cores_per_package, 0, NULL);
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static int cpuid_leaf_b = 1;
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SYSCTL_INT(_hw_vmm_topology, OID_AUTO, cpuid_leaf_b, CTLFLAG_RDTUN,
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&cpuid_leaf_b, 0, NULL);
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/*
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* Round up to the next power of two, if necessary, and then take log2.
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* Returns -1 if argument is zero.
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*/
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static __inline int
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log2(u_int x)
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{
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return (fls(x << (1 - powerof2(x))) - 1);
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}
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int
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x86_emulate_cpuid(struct vm *vm, int vcpu_id,
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uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
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{
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const struct xsave_limits *limits;
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uint64_t cr4;
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int error, enable_invpcid, level, width, x2apic_id;
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unsigned int func, regs[4], logical_cpus;
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enum x2apic_state x2apic_state;
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/*
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* Requests for invalid CPUID levels should map to the highest
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* available level instead.
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*/
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if (cpu_exthigh != 0 && *eax >= 0x80000000) {
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if (*eax > cpu_exthigh)
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*eax = cpu_exthigh;
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} else if (*eax >= 0x40000000) {
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if (*eax > CPUID_VM_HIGH)
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*eax = CPUID_VM_HIGH;
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} else if (*eax > cpu_high) {
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*eax = cpu_high;
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}
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func = *eax;
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/*
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* In general the approach used for CPU topology is to
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* advertise a flat topology where all CPUs are packages with
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* no multi-core or SMT.
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*/
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switch (func) {
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/*
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* Pass these through to the guest
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*/
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case CPUID_0000_0000:
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case CPUID_0000_0002:
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case CPUID_0000_0003:
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case CPUID_8000_0000:
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case CPUID_8000_0002:
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case CPUID_8000_0003:
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case CPUID_8000_0004:
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case CPUID_8000_0006:
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case CPUID_8000_0008:
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cpuid_count(*eax, *ecx, regs);
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break;
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case CPUID_8000_0001:
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/*
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* Hide rdtscp/ia32_tsc_aux until we know how
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* to deal with them.
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*/
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cpuid_count(*eax, *ecx, regs);
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regs[3] &= ~AMDID_RDTSCP;
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break;
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case CPUID_8000_0007:
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cpuid_count(*eax, *ecx, regs);
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/*
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* If the host TSCs are not synchronized across
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* physical cpus then we cannot advertise an
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* invariant tsc to a vcpu.
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*
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* XXX This still falls short because the vcpu
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* can observe the TSC moving backwards as it
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* migrates across physical cpus. But at least
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* it should discourage the guest from using the
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* TSC to keep track of time.
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*/
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if (!smp_tsc)
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regs[3] &= ~AMDPM_TSC_INVARIANT;
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break;
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case CPUID_0000_0001:
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do_cpuid(1, regs);
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error = vm_get_x2apic_state(vm, vcpu_id, &x2apic_state);
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if (error) {
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panic("x86_emulate_cpuid: error %d "
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"fetching x2apic state", error);
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}
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/*
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* Override the APIC ID only in ebx
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*/
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regs[1] &= ~(CPUID_LOCAL_APIC_ID);
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regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT);
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/*
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* Don't expose VMX, SpeedStep or TME capability.
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* Advertise x2APIC capability and Hypervisor guest.
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*/
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regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2);
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regs[2] |= CPUID2_HV;
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if (x2apic_state != X2APIC_DISABLED)
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regs[2] |= CPUID2_X2APIC;
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else
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regs[2] &= ~CPUID2_X2APIC;
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/*
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* Only advertise CPUID2_XSAVE in the guest if
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* the host is using XSAVE.
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*/
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if (!(regs[2] & CPUID2_OSXSAVE))
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regs[2] &= ~CPUID2_XSAVE;
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/*
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* If CPUID2_XSAVE is being advertised and the
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* guest has set CR4_XSAVE, set
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* CPUID2_OSXSAVE.
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*/
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regs[2] &= ~CPUID2_OSXSAVE;
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if (regs[2] & CPUID2_XSAVE) {
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error = vm_get_register(vm, vcpu_id,
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VM_REG_GUEST_CR4, &cr4);
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if (error)
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panic("x86_emulate_cpuid: error %d "
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"fetching %%cr4", error);
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if (cr4 & CR4_XSAVE)
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regs[2] |= CPUID2_OSXSAVE;
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}
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/*
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* Hide monitor/mwait until we know how to deal with
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* these instructions.
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*/
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regs[2] &= ~CPUID2_MON;
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/*
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* Hide the performance and debug features.
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*/
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regs[2] &= ~CPUID2_PDCM;
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/*
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* No TSC deadline support in the APIC yet
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*/
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regs[2] &= ~CPUID2_TSCDLT;
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/*
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* Hide thermal monitoring
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*/
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regs[3] &= ~(CPUID_ACPI | CPUID_TM);
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/*
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* Machine check handling is done in the host.
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* Hide MTRR capability.
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*/
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regs[3] &= ~(CPUID_MCA | CPUID_MCE | CPUID_MTRR);
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/*
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* Hide the debug store capability.
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*/
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regs[3] &= ~CPUID_DS;
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logical_cpus = threads_per_core * cores_per_package;
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regs[1] &= ~CPUID_HTT_CORES;
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regs[1] |= (logical_cpus & 0xff) << 16;
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regs[3] |= CPUID_HTT;
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break;
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case CPUID_0000_0004:
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cpuid_count(*eax, *ecx, regs);
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if (regs[0] || regs[1] || regs[2] || regs[3]) {
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regs[0] &= 0x3ff;
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regs[0] |= (cores_per_package - 1) << 26;
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/*
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* Cache topology:
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* - L1 and L2 are shared only by the logical
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* processors in a single core.
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* - L3 and above are shared by all logical
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* processors in the package.
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*/
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logical_cpus = threads_per_core;
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level = (regs[0] >> 5) & 0x7;
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if (level >= 3)
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logical_cpus *= cores_per_package;
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regs[0] |= (logical_cpus - 1) << 14;
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}
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break;
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case CPUID_0000_0007:
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regs[0] = 0;
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regs[1] = 0;
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regs[2] = 0;
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regs[3] = 0;
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/* leaf 0 */
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if (*ecx == 0) {
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cpuid_count(*eax, *ecx, regs);
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/* Only leaf 0 is supported */
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regs[0] = 0;
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/*
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* Expose known-safe features.
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*/
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regs[1] &= (CPUID_STDEXT_FSGSBASE |
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CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE |
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CPUID_STDEXT_AVX2 | CPUID_STDEXT_BMI2 |
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CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM |
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CPUID_STDEXT_AVX512F |
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CPUID_STDEXT_AVX512PF |
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CPUID_STDEXT_AVX512ER |
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CPUID_STDEXT_AVX512CD);
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regs[2] = 0;
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regs[3] = 0;
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/* Advertise INVPCID if it is enabled. */
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error = vm_get_capability(vm, vcpu_id,
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VM_CAP_ENABLE_INVPCID, &enable_invpcid);
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if (error == 0 && enable_invpcid)
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regs[1] |= CPUID_STDEXT_INVPCID;
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}
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break;
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case CPUID_0000_0006:
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case CPUID_0000_000A:
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/*
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* Handle the access, but report 0 for
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* all options
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*/
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regs[0] = 0;
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regs[1] = 0;
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regs[2] = 0;
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regs[3] = 0;
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break;
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case CPUID_0000_000B:
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/*
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* Processor topology enumeration
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*/
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if (*ecx == 0) {
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logical_cpus = threads_per_core;
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width = log2(logical_cpus);
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level = CPUID_TYPE_SMT;
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x2apic_id = vcpu_id;
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}
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if (*ecx == 1) {
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logical_cpus = threads_per_core *
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cores_per_package;
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width = log2(logical_cpus);
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level = CPUID_TYPE_CORE;
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x2apic_id = vcpu_id;
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}
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if (!cpuid_leaf_b || *ecx >= 2) {
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width = 0;
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logical_cpus = 0;
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level = 0;
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x2apic_id = 0;
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}
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regs[0] = width & 0x1f;
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regs[1] = logical_cpus & 0xffff;
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regs[2] = (level << 8) | (*ecx & 0xff);
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regs[3] = x2apic_id;
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break;
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case CPUID_0000_000D:
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limits = vmm_get_xsave_limits();
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if (!limits->xsave_enabled) {
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regs[0] = 0;
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regs[1] = 0;
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regs[2] = 0;
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regs[3] = 0;
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break;
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}
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cpuid_count(*eax, *ecx, regs);
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switch (*ecx) {
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case 0:
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/*
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* Only permit the guest to use bits
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* that are active in the host in
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* %xcr0. Also, claim that the
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* maximum save area size is
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* equivalent to the host's current
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* save area size. Since this runs
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* "inside" of vmrun(), it runs with
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* the guest's xcr0, so the current
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* save area size is correct as-is.
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*/
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regs[0] &= limits->xcr0_allowed;
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regs[2] = limits->xsave_max_size;
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regs[3] &= (limits->xcr0_allowed >> 32);
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break;
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case 1:
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/* Only permit XSAVEOPT. */
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regs[0] &= CPUID_EXTSTATE_XSAVEOPT;
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regs[1] = 0;
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regs[2] = 0;
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regs[3] = 0;
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break;
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default:
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/*
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* If the leaf is for a permitted feature,
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* pass through as-is, otherwise return
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* all zeroes.
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*/
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if (!(limits->xcr0_allowed & (1ul << *ecx))) {
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regs[0] = 0;
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regs[1] = 0;
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regs[2] = 0;
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regs[3] = 0;
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}
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break;
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}
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break;
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case 0x40000000:
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regs[0] = CPUID_VM_HIGH;
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bcopy(bhyve_id, ®s[1], 4);
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bcopy(bhyve_id + 4, ®s[2], 4);
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bcopy(bhyve_id + 8, ®s[3], 4);
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break;
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default:
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/*
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* The leaf value has already been clamped so
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* simply pass this through, keeping count of
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* how many unhandled leaf values have been seen.
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*/
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atomic_add_long(&bhyve_xcpuids, 1);
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cpuid_count(*eax, *ecx, regs);
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break;
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}
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*eax = regs[0];
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*ebx = regs[1];
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*ecx = regs[2];
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*edx = regs[3];
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return (1);
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}
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