693 lines
18 KiB
C
693 lines
18 KiB
C
/* $Id: ispmbox.h,v 1.7 1998/09/14 23:23:26 mjacob Exp $ */
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/*
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* Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters.
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*
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*---------------------------------------
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* Copyright (c) 1997, 1998 by Matthew Jacob
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* NASA/Ames Research Center
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* All rights reserved.
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*---------------------------------------
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _ISPMBOX_H
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#define _ISPMBOX_H
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/*
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* Mailbox Command Opcodes
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*/
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#define MBOX_NO_OP 0x0000
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#define MBOX_LOAD_RAM 0x0001
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#define MBOX_EXEC_FIRMWARE 0x0002
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#define MBOX_DUMP_RAM 0x0003
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#define MBOX_WRITE_RAM_WORD 0x0004
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#define MBOX_READ_RAM_WORD 0x0005
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#define MBOX_MAILBOX_REG_TEST 0x0006
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#define MBOX_VERIFY_CHECKSUM 0x0007
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#define MBOX_ABOUT_FIRMWARE 0x0008
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/* 9 */
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/* a */
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/* b */
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/* c */
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/* d */
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#define MBOX_CHECK_FIRMWARE 0x000e
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/* f */
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#define MBOX_INIT_REQ_QUEUE 0x0010
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#define MBOX_INIT_RES_QUEUE 0x0011
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#define MBOX_EXECUTE_IOCB 0x0012
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#define MBOX_WAKE_UP 0x0013
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#define MBOX_STOP_FIRMWARE 0x0014
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#define MBOX_ABORT 0x0015
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#define MBOX_ABORT_DEVICE 0x0016
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#define MBOX_ABORT_TARGET 0x0017
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#define MBOX_BUS_RESET 0x0018
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#define MBOX_STOP_QUEUE 0x0019
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#define MBOX_START_QUEUE 0x001a
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#define MBOX_SINGLE_STEP_QUEUE 0x001b
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#define MBOX_ABORT_QUEUE 0x001c
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#define MBOX_GET_DEV_QUEUE_STATUS 0x001d
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/* 1e */
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#define MBOX_GET_FIRMWARE_STATUS 0x001f
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#define MBOX_GET_INIT_SCSI_ID 0x0020
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#define MBOX_GET_SELECT_TIMEOUT 0x0021
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#define MBOX_GET_RETRY_COUNT 0x0022
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#define MBOX_GET_TAG_AGE_LIMIT 0x0023
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#define MBOX_GET_CLOCK_RATE 0x0024
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#define MBOX_GET_ACT_NEG_STATE 0x0025
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#define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
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#define MBOX_GET_SBUS_PARAMS 0x0027
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#define MBOX_GET_TARGET_PARAMS 0x0028
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#define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
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/* 2a */
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/* 2b */
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/* 2c */
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/* 2d */
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/* 2e */
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/* 2f */
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#define MBOX_SET_INIT_SCSI_ID 0x0030
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#define MBOX_SET_SELECT_TIMEOUT 0x0031
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#define MBOX_SET_RETRY_COUNT 0x0032
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#define MBOX_SET_TAG_AGE_LIMIT 0x0033
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#define MBOX_SET_CLOCK_RATE 0x0034
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#define MBOX_SET_ACTIVE_NEG_STATE 0x0035
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#define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
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#define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037
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#define MBOX_SET_PCI_PARAMETERS 0x0037
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#define MBOX_SET_TARGET_PARAMS 0x0038
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#define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
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/* 3a */
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/* 3b */
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/* 3c */
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/* 3d */
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/* 3e */
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/* 3f */
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#define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040
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#define MBOX_WRITE_FOUR_RAM_WORDS 0x0041
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#define MBOX_EXEC_BIOS_IOCB 0x0042
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/* These are for the ISP2100 FC cards */
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#define MBOX_GET_LOOP_ID 0x20
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#define MBOX_EXEC_COMMAND_IOCB_A64 0x54
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#define MBOX_INIT_FIRMWARE 0x60
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#define MBOX_GET_INIT_CONTROL_BLOCK 0x61
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#define MBOX_INIT_LIP 0x62
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#define MBOX_GET_FC_AL_POSITION_MAP 0x63
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#define MBOX_GET_PORT_DB 0x64
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#define MBOX_CLEAR_ACA 0x65
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#define MBOX_TARGET_RESET 0x66
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#define MBOX_CLEAR_TASK_SET 0x67
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#define MBOX_ABORT_TASK_SET 0x68
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#define MBOX_GET_FW_STATE 0x69
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#define MBOX_GET_LINK_STATUS 0x6a
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#define MBOX_INIT_LIP_RESET 0x6c
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#define MBOX_INIT_LIP_LOGIN 0x72
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#define ISP2100_SET_PCI_PARAM 0x00ff
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#define MBOX_BUSY 0x04
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typedef struct {
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u_int16_t param[8];
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} mbreg_t;
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/*
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* Mailbox Command Complete Status Codes
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*/
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#define MBOX_COMMAND_COMPLETE 0x4000
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#define MBOX_INVALID_COMMAND 0x4001
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#define MBOX_HOST_INTERFACE_ERROR 0x4002
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#define MBOX_TEST_FAILED 0x4003
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#define MBOX_COMMAND_ERROR 0x4005
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#define MBOX_COMMAND_PARAM_ERROR 0x4006
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/*
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* Asynchronous event status codes
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*/
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#define ASYNC_BUS_RESET 0x8001
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#define ASYNC_SYSTEM_ERROR 0x8002
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#define ASYNC_RQS_XFER_ERR 0x8003
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#define ASYNC_RSP_XFER_ERR 0x8004
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#define ASYNC_QWAKEUP 0x8005
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#define ASYNC_TIMEOUT_RESET 0x8006
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#define ASYNC_UNSPEC_TMODE 0x8007
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#define ASYNC_EXTMSG_UNDERRUN 0x800A
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#define ASYNC_SCAM_INT 0x800B
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#define ASYNC_HUNG_SCSI 0x800C
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#define ASYNC_KILLED_BUS 0x800D
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#define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */
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#define ASYNC_CMD_CMPLT 0x8020
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#define ASYNC_CTIO_DONE 0x8021
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/* for ISP2100 only */
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#define ASYNC_LIP_OCCURRED 0x8010
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#define ASYNC_LOOP_UP 0x8011
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#define ASYNC_LOOP_DOWN 0x8012
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#define ASYNC_LOOP_RESET 0x8013
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#define ASYNC_PDB_CHANGED 0x8014 /* Port Database Changed */
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#define ASYNC_CHANGE_NOTIFY 0x8015
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/*
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* Command Structure Definitions
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*/
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typedef struct {
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u_int32_t ds_base;
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u_int32_t ds_count;
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} ispds_t;
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typedef struct {
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t rqs_entry_count;
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u_int8_t rqs_entry_type;
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u_int8_t rqs_flags;
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u_int8_t rqs_seqno;
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#else
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u_int8_t rqs_entry_type;
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u_int8_t rqs_entry_count;
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u_int8_t rqs_seqno;
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u_int8_t rqs_flags;
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#endif
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} isphdr_t;
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/* RQS Flag definitions */
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#define RQSFLAG_CONTINUATION 0x01
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#define RQSFLAG_FULL 0x02
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#define RQSFLAG_BADHEADER 0x04
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#define RQSFLAG_BADPACKET 0x08
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/* RQS entry_type definitions */
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#define RQSTYPE_REQUEST 0x01
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#define RQSTYPE_DATASEG 0x02
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#define RQSTYPE_RESPONSE 0x03
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#define RQSTYPE_MARKER 0x04
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#define RQSTYPE_CMDONLY 0x05
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#define RQSTYPE_ATIO 0x06 /* Target Mode */
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#define RQSTYPE_CTIO0 0x07 /* Target Mode */
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#define RQSTYPE_SCAM 0x08
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#define RQSTYPE_A64 0x09
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#define RQSTYPE_A64_CONT 0x0a
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#define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */
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#define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */
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#define RQSTYPE_NOTIFY 0x0d /* Target Mode */
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#define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */
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#define RQSTYPE_CTIO1 0x0f /* Target Mode */
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#define RQSTYPE_STATUS_CONT 0x10
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#define RQSTYPE_T2RQS 0x11
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#define RQSTYPE_T4RQS 0x15
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#define RQSTYPE_ATIO2 0x16
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#define RQSTYPE_CTIO2 0x17
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#define RQSTYPE_CSET0 0x18
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#define RQSTYPE_T3RQS 0x19
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#define RQSTYPE_CTIO3 0x1f
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#define ISP_RQDSEG 4
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typedef struct {
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isphdr_t req_header;
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u_int32_t req_handle;
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t req_target;
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u_int8_t req_lun_trn;
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#else
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u_int8_t req_lun_trn;
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u_int8_t req_target;
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#endif
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u_int16_t req_cdblen;
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#define req_modifier req_cdblen /* marker packet */
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u_int16_t req_flags;
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u_int16_t _res1;
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u_int16_t req_time;
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u_int16_t req_seg_count;
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u_int8_t req_cdb[12];
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ispds_t req_dataseg[ISP_RQDSEG];
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} ispreq_t;
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#define ISP_RQDSEG_T2 3
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typedef struct {
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isphdr_t req_header;
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u_int32_t req_handle;
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t req_target;
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u_int8_t req_lun_trn;
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#else
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u_int8_t req_lun_trn;
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u_int8_t req_target;
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#endif
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u_int16_t _res1;
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u_int16_t req_flags;
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u_int16_t _res2;
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u_int16_t req_time;
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u_int16_t req_seg_count;
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u_int32_t req_cdb[4];
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u_int32_t req_totalcnt;
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ispds_t req_dataseg[ISP_RQDSEG_T2];
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} ispreqt2_t;
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/* req_flag values */
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#define REQFLAG_NODISCON 0x0001
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#define REQFLAG_HTAG 0x0002
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#define REQFLAG_OTAG 0x0004
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#define REQFLAG_STAG 0x0008
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#define REQFLAG_TARGET_RTN 0x0010
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#define REQFLAG_NODATA 0x0000
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#define REQFLAG_DATA_IN 0x0020
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#define REQFLAG_DATA_OUT 0x0040
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#define REQFLAG_DATA_UNKNOWN 0x0060
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#define REQFLAG_DISARQ 0x0100
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#define REQFLAG_FRC_ASYNC 0x0200
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#define REQFLAG_FRC_SYNC 0x0400
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#define REQFLAG_FRC_WIDE 0x0800
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#define REQFLAG_NOPARITY 0x1000
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#define REQFLAG_STOPQ 0x2000
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#define REQFLAG_XTRASNS 0x4000
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#define REQFLAG_PRIORITY 0x8000
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typedef struct {
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isphdr_t req_header;
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u_int32_t req_handle;
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t req_target;
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u_int8_t req_lun_trn;
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#else
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u_int8_t req_lun_trn;
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u_int8_t req_target;
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#endif
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u_int16_t req_cdblen;
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u_int16_t req_flags;
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u_int16_t _res1;
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u_int16_t req_time;
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u_int16_t req_seg_count;
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u_int8_t req_cdb[44];
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} ispextreq_t;
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#define ISP_CDSEG 7
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typedef struct {
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isphdr_t req_header;
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u_int32_t _res1;
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ispds_t req_dataseg[ISP_CDSEG];
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} ispcontreq_t;
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typedef struct {
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isphdr_t req_header;
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u_int32_t _res1;
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t req_target;
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u_int8_t req_lun_trn;
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u_int8_t _res2;
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u_int8_t req_modifier;
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#else
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u_int8_t req_lun_trn;
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u_int8_t req_target;
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u_int8_t req_modifier;
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u_int8_t _res2;
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#endif
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} ispmarkreq_t;
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#define SYNC_DEVICE 0
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#define SYNC_TARGET 1
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#define SYNC_ALL 2
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typedef struct {
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isphdr_t req_header;
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u_int32_t req_handle;
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u_int16_t req_scsi_status;
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u_int16_t req_completion_status;
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u_int16_t req_state_flags;
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u_int16_t req_status_flags;
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u_int16_t req_time;
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u_int16_t req_sense_len;
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u_int32_t req_resid;
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u_int8_t _res1[8];
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u_int8_t req_sense_data[32];
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} ispstatusreq_t;
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/*
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* For Qlogic 2100, the high order byte of SCSI status has
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* additional meaning.
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*/
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#define RQCS_RU 0x800 /* Residual Under */
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#define RQCS_RO 0x400 /* Residual Over */
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#define RQCS_SV 0x200 /* Sense Length Valid */
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#define RQCS_RV 0x100 /* Residual Valid */
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/*
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* Completion Status Codes.
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*/
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#define RQCS_COMPLETE 0x0000
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#define RQCS_INCOMPLETE 0x0001
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#define RQCS_DMA_ERROR 0x0002
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#define RQCS_TRANSPORT_ERROR 0x0003
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#define RQCS_RESET_OCCURRED 0x0004
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#define RQCS_ABORTED 0x0005
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#define RQCS_TIMEOUT 0x0006
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#define RQCS_DATA_OVERRUN 0x0007
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#define RQCS_COMMAND_OVERRUN 0x0008
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#define RQCS_STATUS_OVERRUN 0x0009
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#define RQCS_BAD_MESSAGE 0x000a
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#define RQCS_NO_MESSAGE_OUT 0x000b
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#define RQCS_EXT_ID_FAILED 0x000c
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#define RQCS_IDE_MSG_FAILED 0x000d
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#define RQCS_ABORT_MSG_FAILED 0x000e
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#define RQCS_REJECT_MSG_FAILED 0x000f
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#define RQCS_NOP_MSG_FAILED 0x0010
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#define RQCS_PARITY_ERROR_MSG_FAILED 0x0011
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#define RQCS_DEVICE_RESET_MSG_FAILED 0x0012
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#define RQCS_ID_MSG_FAILED 0x0013
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#define RQCS_UNEXP_BUS_FREE 0x0014
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#define RQCS_DATA_UNDERRUN 0x0015
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#define RQCS_XACT_ERR1 0x0018
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#define RQCS_XACT_ERR2 0x0019
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#define RQCS_XACT_ERR3 0x001A
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#define RQCS_BAD_ENTRY 0x001B
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#define RQCS_QUEUE_FULL 0x001C
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#define RQCS_PHASE_SKIPPED 0x001D
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#define RQCS_ARQS_FAILED 0x001E
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#define RQCS_WIDE_FAILED 0x001F
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#define RQCS_SYNCXFER_FAILED 0x0020
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#define RQCS_LVD_BUSERR 0x0021
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/* 2100 Only Completion Codes */
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#define RQCS_PORT_UNAVAILABLE 0x0028
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#define RQCS_PORT_LOGGED_OUT 0x0029
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#define RQCS_PORT_CHANGED 0x002A
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#define RQCS_PORT_BUSY 0x002B
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/*
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* State Flags (not applicable to 2100)
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*/
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#define RQSF_GOT_BUS 0x0100
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#define RQSF_GOT_TARGET 0x0200
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#define RQSF_SENT_CDB 0x0400
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#define RQSF_XFRD_DATA 0x0800
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#define RQSF_GOT_STATUS 0x1000
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#define RQSF_GOT_SENSE 0x2000
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#define RQSF_XFER_COMPLETE 0x4000
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/*
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* Status Flags (not applicable to 2100)
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*/
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#define RQSTF_DISCONNECT 0x0001
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#define RQSTF_SYNCHRONOUS 0x0002
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#define RQSTF_PARITY_ERROR 0x0004
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#define RQSTF_BUS_RESET 0x0008
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#define RQSTF_DEVICE_RESET 0x0010
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#define RQSTF_ABORTED 0x0020
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#define RQSTF_TIMEOUT 0x0040
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#define RQSTF_NEGOTIATION 0x0080
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/*
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* Target Mode Structures
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*/
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/*
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* Used for Enable LUN and Modify Lun types.
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* (for FC, pre-1.14 FW layout revision).
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*/
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typedef struct {
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isphdr_t req_header;
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u_int32_t req_handle;
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t _reserved0;
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u_int8_t req_lun; /* HOST->FW: LUN to enable */
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#else
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u_int8_t req_lun; /* HOST->FW: LUN to enable */
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u_int8_t _reserved0;
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#endif
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u_int16_t _reserved1[3];
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t _reserved2;
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u_int8_t req_status; /* FW->HOST: Status of Request */
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u_int8_t req_imcount; /* HOST->FW: Immediate Notify Count */
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u_int8_t req_cmdcount; /* HOST->FW: ATIO Count */
|
|
#else
|
|
u_int8_t req_status; /* FW->HOST: Status of Request */
|
|
u_int8_t _reserved2;
|
|
u_int8_t req_cmdcount; /* HOST->FW: ATIO Count */
|
|
u_int8_t req_imcount; /* HOST->FW: Immediate Notify Count */
|
|
#endif
|
|
u_int16_t _reserved3;
|
|
u_int16_t req_timeout; /* HOST->FW: Lun timeout value */
|
|
} isplun_t;
|
|
/* inbound status */
|
|
#define LUN_OKAY 0x01
|
|
#define LUN_ERR 0x04
|
|
#define LUN_NOCAP 0x16
|
|
#define LUN_ENABLED 0x3e
|
|
/* outbound flags */
|
|
#define LUN_INCR_CMD 0x0001
|
|
#define LUN_DECR_CMD 0x0002
|
|
#define LUN_INCR_IMMED 0x0100
|
|
#define LUN_DECR_IMMED 0x0200
|
|
|
|
typedef struct {
|
|
isphdr_t req_header;
|
|
u_int32_t req_handle;
|
|
#if BYTE_ORDER == BIG_ENDIAN
|
|
u_int8_t req_initiator;
|
|
u_int8_t req_lun;
|
|
#else
|
|
u_int8_t req_lun;
|
|
u_int8_t req_initiator;
|
|
#endif
|
|
u_int16_t req_flags; /* NOTIFY_ACK only */
|
|
u_int16_t _reserved1[2];
|
|
u_int16_t req_status;
|
|
u_int16_t req_task_flags;
|
|
u_int16_t req_sequence;
|
|
} ispnotify_t;
|
|
|
|
#define IN_NOCAP 0x16
|
|
#define IN_IDE_RECEIVED 0x33
|
|
#define IN_RSRC_UNAVAIL 0x34
|
|
#define IN_MSG_RECEIVED 0x36
|
|
|
|
typedef struct {
|
|
isphdr_t req_header;
|
|
u_int32_t req_handle;
|
|
#if BYTE_ORDER == BIG_ENDIAN
|
|
u_int8_t req_initiator;
|
|
u_int8_t req_lun;
|
|
#else
|
|
u_int8_t req_lun;
|
|
u_int8_t req_initiator;
|
|
#endif
|
|
u_int16_t req_rxid;
|
|
u_int16_t req_flags;
|
|
u_int16_t req_status;
|
|
#if BYTE_ORDER == BIG_ENDIAN
|
|
u_int8_t req_taskcodes;
|
|
u_int8_t _reserved0;
|
|
u_int8_t req_execodes;
|
|
u_int8_t req_taskflags;
|
|
#else
|
|
u_int8_t _reserved0;
|
|
u_int8_t req_taskcodes;
|
|
u_int8_t req_taskflags;
|
|
u_int8_t req_execodes;
|
|
#endif
|
|
u_int8_t req_cdb[16];
|
|
u_int32_t req_datalen;
|
|
u_int16_t req_scclun;
|
|
u_int16_t _reserved1;;
|
|
u_int16_t req_scsi_status;
|
|
u_int8_t req_sense[18];
|
|
} ispatiot2_t;
|
|
|
|
#define ATIO_PATH_INVALID 0x07
|
|
#define ATIO_PHASE_ERROR 0x14
|
|
#define ATIO_NOCAP 0x16
|
|
#define ATIO_BDR_MSG 0x17
|
|
#define ATIO_CDB_RECEIVED 0x3d
|
|
|
|
#define ATIO_SENSEVALID 0x80
|
|
|
|
/*
|
|
* Continue Target I/O, type 2
|
|
*/
|
|
typedef struct {
|
|
isphdr_t req_header;
|
|
u_int32_t req_handle;
|
|
#if BYTE_ORDER == BIG_ENDIAN
|
|
u_int8_t req_initiator;
|
|
u_int8_t req_lun;
|
|
#else
|
|
u_int8_t req_lun;
|
|
u_int8_t req_initiator;
|
|
#endif
|
|
u_int16_t req_rxid;
|
|
u_int16_t req_flags;
|
|
u_int16_t req_status;
|
|
u_int16_t req_timeout;
|
|
u_int16_t req_seg_count; /* data segment count */
|
|
u_int8_t req_reloff[4]; /* relative offset */
|
|
u_int8_t req_resid[4]; /* residual */
|
|
u_int8_t _reserved0[4];
|
|
union { /* should be offset 0x20 */
|
|
struct {
|
|
u_int16_t _reserved0;
|
|
u_int16_t req_scsi_status;
|
|
u_int32_t req_datalen;
|
|
ispds_t req_dataseg[ISP_RQDSEG_T2];
|
|
} mode0;
|
|
struct {
|
|
u_int16_t req_sense_len;
|
|
u_int16_t req_scsi_status;
|
|
u_int32_t req_response_length;
|
|
u_int8_t req_response[26];
|
|
} mode1;
|
|
struct {
|
|
u_int16_t _reserved0[2];
|
|
u_int32_t req_datalen;
|
|
ispds_t req_fcpiudata;
|
|
} mode2;
|
|
} req_m;
|
|
} ispctiot2_t;
|
|
|
|
#define CTIO_SEND_STATUS 0x8000
|
|
#define CTIO_SEND_DATA 0x0040 /* To initiator */
|
|
#define CTIO_RECV_DATA 0x0080
|
|
#define CTIO_NODATA 0x00C0
|
|
|
|
#define CTIO2_SMODE0 0x0000
|
|
#define CTIO2_SMODE1 0x0001
|
|
#define CTIO2_SMODE2 0x0002
|
|
|
|
#define CTIO2_RESP_VALID 0x0100
|
|
#define CTIO2_STATUS_VALID 0x0200
|
|
#define CTIO2_RSPOVERUN 0x0400
|
|
#define CTIO2_RSPUNDERUN 0x0800
|
|
|
|
|
|
/*
|
|
* FC (ISP2100) specific data structures
|
|
*/
|
|
|
|
/*
|
|
* Initialization Control Block
|
|
*
|
|
* Version One format.
|
|
*/
|
|
typedef struct {
|
|
#if BYTE_ORDER == BIG_ENDIAN
|
|
u_int8_t _reserved0;
|
|
u_int8_t icb_version;
|
|
#else
|
|
u_int8_t icb_version;
|
|
u_int8_t _reserved0;
|
|
#endif
|
|
u_int16_t icb_fwoptions;
|
|
u_int16_t icb_maxfrmlen;
|
|
u_int16_t icb_maxalloc;
|
|
u_int16_t icb_execthrottle;
|
|
#if BYTE_ORDER == BIG_ENDIAN
|
|
u_int8_t icb_retry_delay;
|
|
u_int8_t icb_retry_count;
|
|
#else
|
|
u_int8_t icb_retry_count;
|
|
u_int8_t icb_retry_delay;
|
|
#endif
|
|
u_int8_t icb_nodename[8];
|
|
u_int16_t icb_hardaddr;
|
|
#if BYTE_ORDER == BIG_ENDIAN
|
|
u_int8_t _reserved1;
|
|
u_int8_t icb_iqdevtype;
|
|
#else
|
|
u_int8_t icb_iqdevtype;
|
|
u_int8_t _reserved1;
|
|
#endif
|
|
u_int8_t icb_portname[8];
|
|
u_int16_t icb_rqstout;
|
|
u_int16_t icb_rspnsin;
|
|
u_int16_t icb_rqstqlen;
|
|
u_int16_t icb_rsltqlen;
|
|
u_int16_t icb_rqstaddr[4];
|
|
u_int16_t icb_respaddr[4];
|
|
} isp_icb_t;
|
|
#define ICB_VERSION1 1
|
|
|
|
#define ICBOPT_HARD_ADDRESS (1<<0)
|
|
#define ICBOPT_FAIRNESS (1<<1)
|
|
#define ICBOPT_FULL_DUPLEX (1<<2)
|
|
#define ICBOPT_FAST_POST (1<<3)
|
|
#define ICBOPT_TGT_ENABLE (1<<4)
|
|
#define ICBOPT_INI_DISABLE (1<<5)
|
|
#define ICBOPT_INI_ADISC (1<<6)
|
|
#define ICBOPT_INI_TGTTYPE (1<<7)
|
|
#define ICBOPT_PDBCHANGE_AE (1<<8)
|
|
#define ICBOPT_NOLIP (1<<9)
|
|
#define ICBOPT_SRCHDOWN (1<<10)
|
|
#define ICBOPT_PREVLOOP (1<<11)
|
|
#define ICBOPT_STOP_ON_QFULL (1<<12)
|
|
#define ICBOPT_FULL_LOGIN (1<<13)
|
|
#define ICBOPT_USE_PORTNAME (1<<14)
|
|
|
|
|
|
#define ICB_MIN_FRMLEN 256
|
|
#define ICB_MAX_FRMLEN 2112
|
|
#define ICB_DFLT_FRMLEN 1024
|
|
|
|
#define RQRSP_ADDR0015 0
|
|
#define RQRSP_ADDR1631 1
|
|
#define RQRSP_ADDR3247 2
|
|
#define RQRSP_ADDR4863 3
|
|
|
|
|
|
#if BYTE_ORDER == BIG_ENDIAN
|
|
#define ICB_NNM0 6
|
|
#define ICB_NNM1 7
|
|
#define ICB_NNM2 4
|
|
#define ICB_NNM3 5
|
|
#define ICB_NNM4 2
|
|
#define ICB_NNM5 3
|
|
#define ICB_NNM6 0
|
|
#define ICB_NNM7 1
|
|
#else
|
|
#define ICB_NNM0 7
|
|
#define ICB_NNM1 6
|
|
#define ICB_NNM2 5
|
|
#define ICB_NNM3 4
|
|
#define ICB_NNM4 3
|
|
#define ICB_NNM5 2
|
|
#define ICB_NNM6 1
|
|
#define ICB_NNM7 0
|
|
#endif
|
|
|
|
#define MAKE_NODE_NAME_FROM_WWN(array, wwn) \
|
|
array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \
|
|
array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \
|
|
array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \
|
|
array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \
|
|
array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \
|
|
array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \
|
|
array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \
|
|
array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff)
|
|
|
|
#endif /* _ISPMBOX_H */
|