d993ea4271
- Add a mutex to the softc to protect the softc and device hardware. - Use a private timer to implement a watchdog for tx timeouts and drive the timer for auto negotiation. - Use bus_foo() rather than bus_space_foo() and remove the bus space tag & handle from the softc. - Call bus_setup_intr() after ether_ifattach(). Tested by: Florian Smeets flo of kasimir.com
147 lines
4.2 KiB
C
147 lines
4.2 KiB
C
/*-
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* Copyright (c) 1997 Semen Ustimenko
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Configuration
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*/
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/*#define EPIC_DIAG 1*/
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/*#define EPIC_USEIOSPACE 1*/
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/*#define EPIC_EARLY_RX 1*/
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#ifndef ETHER_MAX_LEN
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#define ETHER_MAX_LEN 1518
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#endif
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#ifndef ETHER_MIN_LEN
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#define ETHER_MIN_LEN 64
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#endif
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#ifndef ETHER_CRC_LEN
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#define ETHER_CRC_LEN 4
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#endif
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#define TX_RING_SIZE 16 /* Leave this a power of 2 */
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#define RX_RING_SIZE 16 /* And this too, to do not */
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/* confuse RX(TX)_RING_MASK */
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#define TX_RING_MASK (TX_RING_SIZE - 1)
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#define RX_RING_MASK (RX_RING_SIZE - 1)
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#define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN)
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#define ETHER_ALIGN 2
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/* This is driver's structure to define EPIC descriptors */
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struct epic_rx_buffer {
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struct mbuf *mbuf; /* mbuf receiving packet */
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bus_dmamap_t map; /* DMA map */
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};
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struct epic_tx_buffer {
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struct mbuf *mbuf; /* mbuf contained packet */
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bus_dmamap_t map; /* DMA map */
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};
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/* PHY, known by tx driver */
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#define EPIC_UNKN_PHY 0x0000
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#define EPIC_QS6612_PHY 0x0001
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#define EPIC_AC101_PHY 0x0002
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#define EPIC_LXT970_PHY 0x0003
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#define EPIC_SERIAL 0x0004
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/* Driver status structure */
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typedef struct {
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struct ifnet *ifp;
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struct resource *res;
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struct resource *irq;
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device_t miibus;
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device_t dev;
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struct callout timer;
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struct mtx lock;
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int tx_timeout;
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void *sc_ih;
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bus_dma_tag_t mtag;
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bus_dma_tag_t rtag;
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bus_dmamap_t rmap;
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bus_dma_tag_t ttag;
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bus_dmamap_t tmap;
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bus_dma_tag_t ftag;
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bus_dmamap_t fmap;
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bus_dmamap_t sparemap;
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struct epic_rx_buffer rx_buffer[RX_RING_SIZE];
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struct epic_tx_buffer tx_buffer[TX_RING_SIZE];
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/* Each element of array MUST be aligned on dword */
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/* and bounded on PAGE_SIZE */
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struct epic_rx_desc *rx_desc;
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struct epic_tx_desc *tx_desc;
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struct epic_frag_list *tx_flist;
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u_int32_t rx_addr;
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u_int32_t tx_addr;
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u_int32_t frag_addr;
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u_int32_t flags;
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u_int32_t tx_threshold;
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u_int32_t txcon;
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u_int32_t miicfg;
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u_int32_t cur_tx;
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u_int32_t cur_rx;
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u_int32_t dirty_tx;
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u_int32_t pending_txs;
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u_int16_t cardvend;
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u_int16_t cardid;
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struct mii_softc *physc;
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u_int32_t phyid;
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int serinst;
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void *pool;
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} epic_softc_t;
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#define EPIC_LOCK(sc) mtx_lock(&(sc)->lock)
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#define EPIC_UNLOCK(sc) mtx_unlock(&(sc)->lock)
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#define EPIC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->lock, MA_OWNED)
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struct epic_type {
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u_int16_t ven_id;
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u_int16_t dev_id;
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char *name;
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};
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#define CSR_WRITE_4(sc, reg, val) \
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bus_write_4((sc)->res, (reg), (val))
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#define CSR_WRITE_2(sc, reg, val) \
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bus_write_2((sc)->res, (reg), (val))
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#define CSR_WRITE_1(sc, reg, val) \
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bus_write_1((sc)->res, (reg), (val))
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#define CSR_READ_4(sc, reg) \
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bus_read_4((sc)->res, (reg))
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#define CSR_READ_2(sc, reg) \
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bus_read_2((sc)->res, (reg))
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#define CSR_READ_1(sc, reg) \
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bus_read_1((sc)->res, (reg))
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#define PHY_READ_2(sc, phy, reg) \
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epic_read_phy_reg((sc), (phy), (reg))
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#define PHY_WRITE_2(sc, phy, reg, val) \
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epic_write_phy_reg((sc), (phy), (reg), (val))
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