Ruslan Bukin b803d0b790 Add support for HiFive Unleashed -- the board with a multi-core RISC-V SoC ... from SiFive, Inc. The first core on this SoC (hart 0) is a 64-bit microcontroller. o Pick a hart to run boot process using hart lottery. This allows to exclude hart 0 from running the boot process. (BBL releases hart 0 after the main harts, so it never wins the lottery). o Renumber CPUs early on boot. Exclude non-MMU cores. Store the original hart ID in struct pcpu. This allows to find out the correct destination for IPIs and remote sfence calls. Thanks to SiFive, Inc for the board provided. Reviewed by: markj Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D20225		2019-05-12 16:17:05 +00:00
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conf	Remove IPSEC from GENERIC due to performance issues	2019-05-09 22:38:15 +00:00
include	Add support for HiFive Unleashed -- the board with a multi-core RISC-V SoC	2019-05-12 16:17:05 +00:00
riscv	Add support for HiFive Unleashed -- the board with a multi-core RISC-V SoC	2019-05-12 16:17:05 +00:00