Adrian Chadd 47ed24efe2 arge: ensure there's enough space in the TX ring before attempting to ... send frames. This matches the other check for space. "enough" is a misnomer, for "reasons". The biggest reason is that the TX ring is actually a circular linked list, with no head/tail pointers. This is just a bit more headroom between head/tail so we have time to schedule frames before we hit where the hardware is at. Ideally this would be tunable and a little larger.		2015-10-30 22:55:41 +00:00
..
apb.c	ACK interrupts on the new SoCs.	2015-01-05 02:00:41 +00:00
apbvar.h
ar71xx_bus_space_reversed.c
ar71xx_bus_space_reversed.h
ar71xx_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar71xx_chip.h
ar71xx_cpudef.h	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar71xx_ehci.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar71xx_fixup.c
ar71xx_fixup.h
ar71xx_gpio.c	Add GPIO function mux configuration for AR934x SoCs.	2015-03-21 06:08:35 +00:00
ar71xx_gpiovar.h	Implement GPIO_GET_BUS() method for all GPIO drivers.	2015-01-31 19:32:14 +00:00
ar71xx_macaddr.c	Begin moving support for board MAC addresses over to being explicitly defined.	2015-03-28 23:40:29 +00:00
ar71xx_macaddr.h	Begin moving support for board MAC addresses over to being explicitly defined.	2015-03-28 23:40:29 +00:00
ar71xx_machdep.c	Populate hw.model with the CPU model information.	2015-07-14 05:14:10 +00:00
ar71xx_ohci.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar71xx_pci_bus_space.c
ar71xx_pci_bus_space.h
ar71xx_pci.c	Remove unused variable leading to compile errors.	2015-09-17 06:07:49 +00:00
ar71xx_setup.c	Add initial Qualcomm Atheros QCA955x SoC support.	2015-01-05 02:06:26 +00:00
ar71xx_setup.h	add QCA955x SoC types.	2015-01-05 01:59:44 +00:00
ar71xx_spi.c
ar71xx_wdog.c
ar71xxreg.h	Add a MII mode for SGMII.	2015-03-02 01:23:59 +00:00
ar91xx_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar91xx_chip.h
ar91xxreg.h
ar724x_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar724x_chip.h
ar724x_pci.c	Remove more unused variables leading to compile time errors.	2015-09-17 12:04:41 +00:00
ar724xreg.h	Note that the AR724x PCIe registers are actually from the PCI_CTRL	2015-03-21 05:59:45 +00:00
ar933x_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar933x_chip.h
ar933x_uart.h
ar933xreg.h
ar934x_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
ar934x_chip.h
ar934x_nfcreg.h
ar934xreg.h
files.ar71xx	Add initial support for the QCA955x PCIe host controller.	2015-05-19 05:31:58 +00:00
if_arge.c	arge: ensure there's enough space in the TX ring before attempting to	2015-10-30 22:55:41 +00:00
if_argevar.h	arge: do a read-after-write on all arge register writes, not just MDIO writes.	2015-10-30 22:53:30 +00:00
pcf2123_rtc.c
pcf2123reg.h
qca955x_chip.c	Reshuffle all of the DDR flush operations into a single switch/mux,	2015-07-04 03:05:57 +00:00
qca955x_chip.h	Add initial Qualcomm Atheros QCA955x SoC support.	2015-01-05 02:06:26 +00:00
qca955x_pci.c	Remove more unused variables leading to compile time errors.	2015-09-17 12:04:41 +00:00
qca955xreg.h	Oops - fix typo.	2015-07-03 07:00:24 +00:00
std.ar71xx
uart_bus_ar71xx.c
uart_bus_ar933x.c
uart_cpu_ar71xx.c
uart_cpu_ar933x.c
uart_dev_ar933x.c	Add support for the uart classes to set their default register shift value.	2015-04-11 17:16:23 +00:00
uart_dev_ar933x.h