3a6a9a3bcc
from the git tree. This merges a lot that we're not using, but there's too many files to be selective and have a hope of catching everything. If there are conflicts with the rest of the tree, we'll resolve them on a case by case basis. MFC after: 2 weeks Sponsored by: Netflix, Inc.
63 lines
2.0 KiB
Plaintext
63 lines
2.0 KiB
Plaintext
/*
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* Copyright (C) 2013,2014 Russell King
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*
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* This describes the hookup for an AR8035 to the iMX6 on the SolidRun
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* MicroSOM.
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*/
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
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phy-mode = "rgmii";
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phy-reset-duration = <2>;
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phy-reset-gpios = <&gpio4 15 0>;
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status = "okay";
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};
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&iomuxc {
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enet {
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pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
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fsl,pins = <
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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/* AR8035 reset */
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MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
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/* AR8035 interrupt */
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MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x80000000
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/* GPIO16 -> AR8035 25MHz */
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MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
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MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
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MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
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MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
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MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
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MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
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MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
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/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
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/* AR8035 pin strapping: IO voltage: pull up */
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MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
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/* AR8035 pin strapping: PHYADDR#0: pull down */
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MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
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/* AR8035 pin strapping: PHYADDR#1: pull down */
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MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
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/* AR8035 pin strapping: MODE#1: pull up */
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MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
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/* AR8035 pin strapping: MODE#3: pull up */
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MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
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/* AR8035 pin strapping: MODE#0: pull down */
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MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
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/*
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* As the RMII pins are also connected to RGMII
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* so that an AR8030 can be placed, set these
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* to high-z with the same pulls as above.
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* Use the GPIO settings to avoid changing the
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* input select registers.
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*/
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MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000
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MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000
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MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000
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>;
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};
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};
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};
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