2cf9911fc1
this on the branch.
Original commit message:
Initial bhyve native graphics support.
This adds emulations for a raw framebuffer device, PS2 keyboard/mouse,
XHCI USB controller and a USB tablet.
A simple VNC server is provided for keyboard/mouse input, and graphics
output.
A VGA emulation is included, but is currently disconnected until an
additional bhyve change to block out VGA memory is committed.
Credits:
- raw framebuffer, VNC server, XHCI controller, USB bus/device emulation
and UEFI f/w support by Leon Dang
- VGA, console/g, initial VNC server by tychon@
- PS2 keyboard/mouse jointly done by tychon@ and Leon Dang
- hypervisor framebuffer mem support by neel@
Tested by: Michael Dexter, in a number of revisions of this code.
With the appropriate UEFI image, FreeBSD, Windows and Linux guests can
installed and run in graphics mode using the UEFI/GOP framebuffer.
Approved by: re (gjb)
354 lines
13 KiB
C
354 lines
13 KiB
C
/*-
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* Copyright (c) 2014 Leon Dang <ldang@nahannisys.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _PCI_XHCI_H_
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#define _PCI_XHCI_H_
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#define PCI_USBREV 0x60 /* USB protocol revision */
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enum { /* dsc_slotstate */
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XHCI_ST_DISABLED,
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XHCI_ST_ENABLED,
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XHCI_ST_DEFAULT,
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XHCI_ST_ADDRESSED,
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XHCI_ST_CONFIGURED,
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XHCI_ST_MAX
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};
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enum {
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XHCI_ST_SLCTX_DISABLED,
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XHCI_ST_SLCTX_DEFAULT,
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XHCI_ST_SLCTX_ADDRESSED,
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XHCI_ST_SLCTX_CONFIGURED
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};
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enum {
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XHCI_ST_EPCTX_DISABLED,
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XHCI_ST_EPCTX_RUNNING,
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XHCI_ST_EPCTX_HALTED,
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XHCI_ST_EPCTX_STOPPED,
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XHCI_ST_EPCTX_ERROR
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};
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#define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128)
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#define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */
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#define XHCI_MAX_SCRATCHPADS 32
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#define XHCI_MAX_EVENTS (16 * 13)
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#define XHCI_MAX_COMMANDS (16 * 1)
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#define XHCI_MAX_RSEG 1
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#define XHCI_MAX_TRANSFERS 4
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#if USB_MAX_EP_STREAMS == 8
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#define XHCI_MAX_STREAMS 8
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#define XHCI_MAX_STREAMS_LOG 3
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#elif USB_MAX_EP_STREAMS == 1
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#define XHCI_MAX_STREAMS 1
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#define XHCI_MAX_STREAMS_LOG 0
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#else
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#error "The USB_MAX_EP_STREAMS value is not supported."
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#endif
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#define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */
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#define XHCI_DEV_CTX_ALIGN 64 /* bytes */
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#define XHCI_INPUT_CTX_ALIGN 64 /* bytes */
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#define XHCI_SLOT_CTX_ALIGN 32 /* bytes */
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#define XHCI_ENDP_CTX_ALIGN 32 /* bytes */
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#define XHCI_STREAM_CTX_ALIGN 16 /* bytes */
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#define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */
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#define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */
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#define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */
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#define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */
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#define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE
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#define XHCI_TRB_ALIGN 16 /* bytes */
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#define XHCI_TD_ALIGN 64 /* bytes */
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#define XHCI_PAGE_SIZE 4096 /* bytes */
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struct xhci_slot_ctx {
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volatile uint32_t dwSctx0;
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#define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF)
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#define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF)
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#define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20)
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#define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF)
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#define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25)
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#define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1)
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#define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26)
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#define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1)
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#define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27)
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#define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F)
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volatile uint32_t dwSctx1;
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#define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF)
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#define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF)
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#define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16)
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#define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF)
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#define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24)
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#define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF)
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volatile uint32_t dwSctx2;
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#define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF)
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#define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF)
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#define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8)
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#define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF)
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#define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16)
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#define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3)
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#define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22)
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#define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF)
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volatile uint32_t dwSctx3;
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#define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF)
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#define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF)
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#define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27)
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#define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F)
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volatile uint32_t dwSctx4;
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volatile uint32_t dwSctx5;
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volatile uint32_t dwSctx6;
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volatile uint32_t dwSctx7;
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};
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struct xhci_endp_ctx {
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volatile uint32_t dwEpCtx0;
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#define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7)
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#define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7)
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#define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8)
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#define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3)
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#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10)
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#define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F)
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#define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15)
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#define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1)
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#define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16)
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#define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF)
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volatile uint32_t dwEpCtx1;
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#define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1)
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#define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3)
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#define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3)
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#define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7)
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#define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7)
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#define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1)
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#define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8)
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#define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF)
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#define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16)
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#define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF)
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volatile uint64_t qwEpCtx2;
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#define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1)
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#define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1)
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#define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U
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volatile uint32_t dwEpCtx4;
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#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF)
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#define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF)
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#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16)
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#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF)
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volatile uint32_t dwEpCtx5;
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volatile uint32_t dwEpCtx6;
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volatile uint32_t dwEpCtx7;
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};
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struct xhci_input_ctx {
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#define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU
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volatile uint32_t dwInCtx0;
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#define XHCI_INCTX_0_DROP_MASK(n) (1U << (n))
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volatile uint32_t dwInCtx1;
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#define XHCI_INCTX_1_ADD_MASK(n) (1U << (n))
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volatile uint32_t dwInCtx2;
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volatile uint32_t dwInCtx3;
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volatile uint32_t dwInCtx4;
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volatile uint32_t dwInCtx5;
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volatile uint32_t dwInCtx6;
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volatile uint32_t dwInCtx7;
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};
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struct xhci_input_dev_ctx {
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struct xhci_input_ctx ctx_input;
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union {
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struct xhci_slot_ctx u_slot;
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struct xhci_endp_ctx u_ep[XHCI_MAX_ENDPOINTS];
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} ctx_dev_slep;
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};
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struct xhci_dev_ctx {
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union {
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struct xhci_slot_ctx u_slot;
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struct xhci_endp_ctx u_ep[XHCI_MAX_ENDPOINTS];
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} ctx_dev_slep;
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} __aligned(XHCI_DEV_CTX_ALIGN);
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#define ctx_slot ctx_dev_slep.u_slot
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#define ctx_ep ctx_dev_slep.u_ep
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struct xhci_stream_ctx {
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volatile uint64_t qwSctx0;
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#define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1)
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#define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1)
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#define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1)
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#define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7)
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#define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0
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#define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1
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#define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2
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#define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3
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#define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4
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#define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5
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#define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6
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#define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7
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#define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U
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volatile uint32_t dwSctx2;
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volatile uint32_t dwSctx3;
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};
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struct xhci_trb {
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volatile uint64_t qwTrb0;
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#define XHCI_TRB_0_DIR_IN_MASK (0x80ULL << 0)
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#define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48)
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volatile uint32_t dwTrb2;
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#define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF)
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#define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24)
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#define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F)
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#define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17)
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#define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF)
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#define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF)
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#define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF)
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#define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF)
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#define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF)
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#define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22)
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#define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF)
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#define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16)
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volatile uint32_t dwTrb3;
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#define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F)
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#define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10)
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#define XHCI_TRB_3_CYCLE_BIT (1U << 0)
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#define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */
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#define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */
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#define XHCI_TRB_3_ISP_BIT (1U << 2)
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#define XHCI_TRB_3_ED_BIT (1U << 2)
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#define XHCI_TRB_3_NSNOOP_BIT (1U << 3)
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#define XHCI_TRB_3_CHAIN_BIT (1U << 4)
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#define XHCI_TRB_3_IOC_BIT (1U << 5)
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#define XHCI_TRB_3_IDT_BIT (1U << 6)
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#define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3)
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#define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7)
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#define XHCI_TRB_3_BEI_BIT (1U << 9)
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#define XHCI_TRB_3_DCEP_BIT (1U << 9)
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#define XHCI_TRB_3_PRSV_BIT (1U << 9)
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#define XHCI_TRB_3_BSR_BIT (1U << 9)
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#define XHCI_TRB_3_TRT_MASK (3U << 16)
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#define XHCI_TRB_3_TRT_NONE (0U << 16)
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#define XHCI_TRB_3_TRT_OUT (2U << 16)
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#define XHCI_TRB_3_TRT_IN (3U << 16)
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#define XHCI_TRB_3_DIR_IN (1U << 16)
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#define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF)
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#define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16)
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#define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F)
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#define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16)
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#define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF)
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#define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20)
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#define XHCI_TRB_3_ISO_SIA_BIT (1U << 31)
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#define XHCI_TRB_3_SUSP_EP_BIT (1U << 23)
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#define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF)
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#define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24)
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/* Commands */
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#define XHCI_TRB_TYPE_RESERVED 0x00
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#define XHCI_TRB_TYPE_NORMAL 0x01
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#define XHCI_TRB_TYPE_SETUP_STAGE 0x02
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#define XHCI_TRB_TYPE_DATA_STAGE 0x03
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#define XHCI_TRB_TYPE_STATUS_STAGE 0x04
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#define XHCI_TRB_TYPE_ISOCH 0x05
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#define XHCI_TRB_TYPE_LINK 0x06
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#define XHCI_TRB_TYPE_EVENT_DATA 0x07
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#define XHCI_TRB_TYPE_NOOP 0x08
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#define XHCI_TRB_TYPE_ENABLE_SLOT 0x09
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#define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A
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#define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B
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#define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C
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#define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D
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#define XHCI_TRB_TYPE_RESET_EP 0x0E
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#define XHCI_TRB_TYPE_STOP_EP 0x0F
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#define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10
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#define XHCI_TRB_TYPE_RESET_DEVICE 0x11
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#define XHCI_TRB_TYPE_FORCE_EVENT 0x12
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#define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13
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#define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14
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#define XHCI_TRB_TYPE_GET_PORT_BW 0x15
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#define XHCI_TRB_TYPE_FORCE_HEADER 0x16
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#define XHCI_TRB_TYPE_NOOP_CMD 0x17
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/* Events */
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#define XHCI_TRB_EVENT_TRANSFER 0x20
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#define XHCI_TRB_EVENT_CMD_COMPLETE 0x21
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#define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22
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#define XHCI_TRB_EVENT_BW_REQUEST 0x23
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#define XHCI_TRB_EVENT_DOORBELL 0x24
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#define XHCI_TRB_EVENT_HOST_CTRL 0x25
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#define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26
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#define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27
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/* Error codes */
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#define XHCI_TRB_ERROR_INVALID 0x00
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#define XHCI_TRB_ERROR_SUCCESS 0x01
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#define XHCI_TRB_ERROR_DATA_BUF 0x02
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#define XHCI_TRB_ERROR_BABBLE 0x03
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#define XHCI_TRB_ERROR_XACT 0x04
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#define XHCI_TRB_ERROR_TRB 0x05
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#define XHCI_TRB_ERROR_STALL 0x06
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#define XHCI_TRB_ERROR_RESOURCE 0x07
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#define XHCI_TRB_ERROR_BANDWIDTH 0x08
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#define XHCI_TRB_ERROR_NO_SLOTS 0x09
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#define XHCI_TRB_ERROR_STREAM_TYPE 0x0A
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#define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B
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#define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C
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#define XHCI_TRB_ERROR_SHORT_PKT 0x0D
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#define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E
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#define XHCI_TRB_ERROR_RING_OVERRUN 0x0F
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#define XHCI_TRB_ERROR_VF_RING_FULL 0x10
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#define XHCI_TRB_ERROR_PARAMETER 0x11
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#define XHCI_TRB_ERROR_BW_OVERRUN 0x12
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#define XHCI_TRB_ERROR_CONTEXT_STATE 0x13
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#define XHCI_TRB_ERROR_NO_PING_RESP 0x14
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#define XHCI_TRB_ERROR_EV_RING_FULL 0x15
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#define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16
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#define XHCI_TRB_ERROR_MISSED_SERVICE 0x17
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#define XHCI_TRB_ERROR_CMD_RING_STOP 0x18
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#define XHCI_TRB_ERROR_CMD_ABORTED 0x19
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#define XHCI_TRB_ERROR_STOPPED 0x1A
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#define XHCI_TRB_ERROR_LENGTH 0x1B
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#define XHCI_TRB_ERROR_BAD_MELAT 0x1D
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#define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F
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#define XHCI_TRB_ERROR_EVENT_LOST 0x20
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#define XHCI_TRB_ERROR_UNDEFINED 0x21
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#define XHCI_TRB_ERROR_INVALID_SID 0x22
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#define XHCI_TRB_ERROR_SEC_BW 0x23
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#define XHCI_TRB_ERROR_SPLIT_XACT 0x24
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} __aligned(4);
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struct xhci_dev_endpoint_trbs {
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struct xhci_trb trb[(XHCI_MAX_STREAMS *
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XHCI_MAX_TRANSFERS) + XHCI_MAX_STREAMS];
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};
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struct xhci_event_ring_seg {
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volatile uint64_t qwEvrsTablePtr;
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volatile uint32_t dwEvrsTableSize;
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volatile uint32_t dwEvrsReserved;
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};
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#endif /* _PCI_XHCI_H_ */
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