209 lines
5.1 KiB
C
209 lines
5.1 KiB
C
/*-
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* Copyright (c) 2011 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/smp.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <arm/mv/mvwin.h>
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static int platform_get_ncpus(void);
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#define MV_AXP_CPU_DIVCLK_BASE (MV_BASE + 0x18700)
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#define CPU_DIVCLK_CTRL0 0x00
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#define CPU_DIVCLK_CTRL2_RATIO_FULL0 0x08
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#define CPU_DIVCLK_CTRL2_RATIO_FULL1 0x0c
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#define MV_COHERENCY_FABRIC_BASE (MV_MBUS_BRIDGE_BASE + 0x200)
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#define COHER_FABRIC_CTRL 0x00
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#define COHER_FABRIC_CONF 0x04
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#define CPU_PMU(x) (MV_BASE + 0x22100 + (0x100 * (x)))
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#define CPU_PMU_BOOT 0x24
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#define MP (MV_BASE + 0x20800)
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#define MP_SW_RESET(x) ((x) * 8)
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#define CPU_RESUME_CONTROL (0x20988)
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/* Coherency Fabric registers */
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static uint32_t
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read_coher_fabric(uint32_t reg)
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{
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return (bus_space_read_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg));
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}
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static void
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write_coher_fabric(uint32_t reg, uint32_t val)
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{
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bus_space_write_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg, val);
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}
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/* Coherency Fabric registers */
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static uint32_t
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read_cpu_clkdiv(uint32_t reg)
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{
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return (bus_space_read_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg));
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}
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static void
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write_cpu_clkdiv(uint32_t reg, uint32_t val)
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{
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bus_space_write_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg, val);
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}
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void
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platform_mp_setmaxid(void)
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{
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mp_maxid = 3;
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}
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int
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platform_mp_probe(void)
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{
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mp_ncpus = platform_get_ncpus();
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return (mp_ncpus > 1);
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}
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void
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platform_mp_init_secondary(void)
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{
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}
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void mpentry(void);
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void mptramp(void);
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static void
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initialize_coherency_fabric(void)
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{
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uint32_t val, cpus, mask;
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cpus = platform_get_ncpus();
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mask = (1 << cpus) - 1;
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val = read_coher_fabric(COHER_FABRIC_CTRL);
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val |= (mask << 24);
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write_coher_fabric(COHER_FABRIC_CTRL, val);
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val = read_coher_fabric(COHER_FABRIC_CONF);
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val |= (mask << 24);
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write_coher_fabric(COHER_FABRIC_CONF, val);
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}
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void
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platform_mp_start_ap(void)
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{
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uint32_t reg, *ptr, cpu_num;
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/* Copy boot code to SRAM */
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*((unsigned int*)(0xf1020240)) = 0xffff0101;
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*((unsigned int*)(0xf1008500)) = 0xffff0003;
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pmap_kenter_nocache(0x880f0000, 0xffff0000);
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reg = 0x880f0000;
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for (ptr = (uint32_t *)mptramp; ptr < (uint32_t *)mpentry;
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ptr++, reg += 4)
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*((uint32_t *)reg) = *ptr;
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if (mp_ncpus > 1) {
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reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0);
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reg &= 0x00ffffff;
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reg |= 0x01000000;
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write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0, reg);
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}
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if (mp_ncpus > 2) {
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reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);
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reg &= 0xff00ffff;
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reg |= 0x00010000;
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write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg);
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}
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if (mp_ncpus > 3) {
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reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);
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reg &= 0x00ffffff;
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reg |= 0x01000000;
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write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg);
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}
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reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0);
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reg |= ((0x1 << (mp_ncpus - 1)) - 1) << 21;
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write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
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reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0);
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reg |= 0x01000000;
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write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
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DELAY(100);
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reg &= ~(0xf << 21);
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write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
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DELAY(100);
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bus_space_write_4(fdtbus_bs_tag, MV_BASE, CPU_RESUME_CONTROL, 0);
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for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )
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bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT,
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pmap_kextract((vm_offset_t)mpentry));
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cpu_idcache_wbinv_all();
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for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )
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bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0);
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/* XXX: Temporary workaround for hangup after releasing AP's */
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wmb();
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DELAY(10);
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initialize_coherency_fabric();
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}
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static int
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platform_get_ncpus(void)
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{
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return ((read_coher_fabric(COHER_FABRIC_CONF) & 0xf) + 1);
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}
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void
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platform_ipi_send(cpuset_t cpus, u_int ipi)
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{
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pic_ipi_send(cpus, ipi);
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}
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