7a58bf0443
Enabling HvCallSetVpRegisters and HvCallGetVpRegisters for hypercalls to read and write to specific MSRs. This is required for implementing wrmsr and rdmsr, which is required for Hyper-V vmbus driver for ARM64. Also we need to use arm smccc hvc 1.2 version as we need to access registers beyond X0-X3 for HvCallGetVpRegisters. Currently scoping it only for Hyper-V. Reviewed by: lwhsu, andrew, whu Tested by: Souradeep Chakrabarti <schakrabarti@microsoft.com> Signed-off-by: Souradeep Chakrabarti <schakrabarti@microsoft.com> Sponsored by: Microsoft Differential Revision: https://reviews.freebsd.org/D36256
120 lines
3.9 KiB
C
120 lines
3.9 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2018 Andrew Turner
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _PSCI_SMCCC_H_
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#define _PSCI_SMCCC_H_
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#define SMCCC_VERSION_MAJOR(ver) (((ver) >> 16) & 0x7fff)
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#define SMCCC_VERSION_MINOR(ver) ((ver) & 0xffff)
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#define SMCCC_FUNC_ID(type, call_conv, range, func) \
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(((type) << 31) | \
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((call_conv) << 30) | \
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(((range) & 0x3f) << 24) | \
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((func) & 0xffff))
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#define SMCCC_YIELDING_CALL 0
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#define SMCCC_FAST_CALL 1
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#define SMCCC_32BIT_CALL 0
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#define SMCCC_64BIT_CALL 1
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#define SMCCC_ARM_ARCH_CALLS 0
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#define SMCCC_CPU_SERVICE_CALLS 1
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#define SMCCC_SIP_SERVICE_CALLS 2
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#define SMCCC_OEM_SERVICE_CALLS 3
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#define SMCCC_STD_SECURE_SERVICE_CALLS 4
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#define SMCCC_STD_HYP_SERVICE_CALLS 5
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#define SMCCC_VENDOR_HYP_SERVICE_CALLS 6
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struct arm_smccc_res {
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register_t a0;
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register_t a1;
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register_t a2;
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register_t a3;
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};
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/*
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* Arm Architecture Calls.
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* These are documented in the document ARM DEN 0070A.
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*/
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#define SMCCC_VERSION \
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SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_32BIT_CALL, 0, 0)
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#define SMCCC_ARCH_FEATURES \
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SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_32BIT_CALL, 0, 1)
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#define SMCCC_ARCH_WORKAROUND_1 \
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SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_32BIT_CALL, 0, 0x8000)
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#define SMCCC_ARCH_WORKAROUND_2 \
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SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_32BIT_CALL, 0, 0x7fff)
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/* The return values from ARM DEN 0070A. */
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#define SMCCC_RET_SUCCESS 0
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#define SMCCC_RET_NOT_SUPPORTED -1
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#define SMCCC_RET_NOT_REQUIRED -2
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int32_t smccc_arch_features(uint32_t);
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int smccc_arch_workaround_1(void);
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int smccc_arch_workaround_2(int);
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int arm_smccc_smc(register_t, register_t, register_t, register_t, register_t,
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register_t, register_t, register_t, struct arm_smccc_res *res);
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int arm_smccc_hvc(register_t, register_t, register_t, register_t, register_t,
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register_t, register_t, register_t, struct arm_smccc_res *res);
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struct arm_smccc_1_2_regs {
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register_t a0;
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register_t a1;
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register_t a2;
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register_t a3;
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register_t a4;
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register_t a5;
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register_t a6;
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register_t a7;
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register_t a8;
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register_t a9;
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register_t a10;
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register_t a11;
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register_t a12;
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register_t a13;
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register_t a14;
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register_t a15;
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register_t a16;
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register_t a17;
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};
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int arm_smccc_1_2_hvc(const struct arm_smccc_1_2_regs *args,
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struct arm_smccc_1_2_regs *res);
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int arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,
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struct arm_smccc_1_2_regs *res);
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#endif /* _PSCI_SMCCC_H_ */
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