4ad6106939
* Support for sam9 "EMAC" controller.
* Support for rmii interface to phy.
at91.c & at91sam9.c:
* Eliminate separate at91sam9.c file.
* Add new devices to at91sam9_devs table.
at91_machdep.c & at at91sam9_machdep.c:
* Automatic chip type determination.
* Remove compile time chip dependencies.
* Eliminate separate at91sam9_machdep.c file.
at91_pmc.c:
* Corrected support for all of the sam926? and sam9g20 chips.
* Remove compile time chip dependencies.
My apologies to Greg for taking so long to take care of it.
582 lines
13 KiB
C
582 lines
13 KiB
C
/*-
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|
* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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* Copyright (c) 2010 Greg Ansley. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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|
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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|
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/time.h>
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#include <sys/bus.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/timetc.h>
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|
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/resource.h>
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#include <machine/frame.h>
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#include <machine/intr.h>
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#include <arm/at91/at91reg.h>
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#include <arm/at91/at91var.h>
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#include <arm/at91/at91_pmcreg.h>
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#include <arm/at91/at91_pmcvar.h>
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static struct at91_pmc_softc {
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bus_space_tag_t sc_st;
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bus_space_handle_t sc_sh;
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struct resource *mem_res; /* Memory resource */
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device_t dev;
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unsigned int main_clock_hz;
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uint32_t pllb_init;
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} *pmc_softc;
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|
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MALLOC_DECLARE(M_PMC);
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MALLOC_DEFINE(M_PMC, "at91_pmc_clocks", "AT91 PMC Clock descriptors");
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|
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static void at91_pmc_set_pllb_mode(struct at91_pmc_clock *, int);
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static void at91_pmc_set_sys_mode(struct at91_pmc_clock *, int);
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static void at91_pmc_set_periph_mode(struct at91_pmc_clock *, int);
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static void at91_pmc_clock_alias(const char *name, const char *alias);
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|
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static struct at91_pmc_clock slck = {
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.name = "slck", // 32,768 Hz slow clock
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.hz = 32768,
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.refcnt = 1,
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.id = 0,
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.primary = 1,
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};
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|
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/*
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* NOTE: Clocks for "ordinary peripheral" devices e.g. spi0, udp0, uhp0 etc.
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* are now created automatically. Only "system" clocks need be defined here.
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*/
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static struct at91_pmc_clock main_ck = {
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.name = "main", // Main clock
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.refcnt = 0,
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.id = 1,
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.primary = 1,
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.pmc_mask = PMC_IER_MOSCS,
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};
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|
|
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static struct at91_pmc_clock plla = {
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.name = "plla", // PLLA Clock, used for CPU clocking
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.parent = &main_ck,
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.refcnt = 1,
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.id = 0,
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.primary = 1,
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.pll = 1,
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.pmc_mask = PMC_IER_LOCKA,
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};
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static struct at91_pmc_clock pllb = {
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.name = "pllb", // PLLB Clock, used for USB functions
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.parent = &main_ck,
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.refcnt = 0,
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.id = 0,
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.primary = 1,
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.pll = 1,
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.pmc_mask = PMC_IER_LOCKB,
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.set_mode = &at91_pmc_set_pllb_mode,
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};
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static struct at91_pmc_clock udpck = {
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.name = "udpck",
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.parent = &pllb,
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.pmc_mask = PMC_SCER_UDP,
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.set_mode = at91_pmc_set_sys_mode
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};
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static struct at91_pmc_clock uhpck = {
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.name = "uhpck",
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.parent = &pllb,
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.pmc_mask = PMC_SCER_UHP,
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.set_mode = at91_pmc_set_sys_mode
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};
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static struct at91_pmc_clock mck = {
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.name = "mck", // Master (Peripheral) Clock
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.pmc_mask = PMC_IER_MCKRDY,
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.refcnt = 0,
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};
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static struct at91_pmc_clock cpu = {
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.name = "cpu", // CPU Clock
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.parent = &plla,
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.pmc_mask = PMC_SCER_PCK,
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.refcnt = 0,
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};
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/* "+32" or the automatic peripheral clocks */
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static struct at91_pmc_clock *clock_list[16+32] = {
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&slck,
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&main_ck,
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&plla,
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&pllb,
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&udpck,
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&uhpck,
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&mck,
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&cpu
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};
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#if !defined(AT91C_MAIN_CLOCK)
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static const unsigned int at91_mainf_tbl[] = {
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3000000, 3276800, 3686400, 3840000, 4000000,
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4433619, 4915200, 5000000, 5242880, 6000000,
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6144000, 6400000, 6553600, 7159090, 7372800,
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7864320, 8000000, 9830400, 10000000, 11059200,
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12000000, 12288000, 13560000, 14318180, 14745600,
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16000000, 17344700, 18432000, 20000000
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};
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#define MAINF_TBL_LEN (sizeof(at91_mainf_tbl) / sizeof(*at91_mainf_tbl))
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#endif
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static inline uint32_t
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RD4(struct at91_pmc_softc *sc, bus_size_t off)
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{
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return (bus_read_4(sc->mem_res, off));
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}
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static inline void
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WR4(struct at91_pmc_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_write_4(sc->mem_res, off, val);
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}
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|
void
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at91_pmc_set_pllb_mode(struct at91_pmc_clock *clk, int on)
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{
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struct at91_pmc_softc *sc = pmc_softc;
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uint32_t value;
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|
if (on) {
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on = PMC_IER_LOCKB;
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value = sc->pllb_init;
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} else {
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value = 0;
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|
}
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|
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|
/* Workaround RM9200 Errata #26 */
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if (at91_is_rm92() &&
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((value ^ RD4(sc, CKGR_PLLBR)) & 0x03f0ff) != 0) {
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WR4(sc, CKGR_PLLBR, value ^ 1);
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while ((RD4(sc, PMC_SR) & PMC_IER_LOCKB) != on)
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|
continue;
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}
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|
WR4(sc, CKGR_PLLBR, value);
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while ((RD4(sc, PMC_SR) & PMC_IER_LOCKB) != on)
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continue;
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}
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static void
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at91_pmc_set_sys_mode(struct at91_pmc_clock *clk, int on)
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{
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struct at91_pmc_softc *sc = pmc_softc;
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WR4(sc, on ? PMC_SCER : PMC_SCDR, clk->pmc_mask);
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if (on)
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while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) != clk->pmc_mask)
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continue;
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else
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while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) == clk->pmc_mask)
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continue;
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}
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static void
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at91_pmc_set_periph_mode(struct at91_pmc_clock *clk, int on)
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{
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struct at91_pmc_softc *sc = pmc_softc;
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WR4(sc, on ? PMC_PCER : PMC_PCDR, clk->pmc_mask);
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if (on)
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while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) != clk->pmc_mask)
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continue;
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else
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while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) == clk->pmc_mask)
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continue;
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}
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struct at91_pmc_clock *
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at91_pmc_clock_add(const char *name, uint32_t irq, struct at91_pmc_clock *parent)
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{
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struct at91_pmc_clock *clk;
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int i, buflen;
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clk = malloc(sizeof(*clk), M_PMC, M_NOWAIT | M_ZERO);
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if (clk == NULL)
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goto err;
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buflen = strlen(name) + 1;
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clk->name = malloc(buflen, M_PMC, M_NOWAIT);
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if (clk->name == NULL)
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goto err;
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strlcpy(clk->name, name, buflen);
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clk->pmc_mask = 1 << irq;
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clk->set_mode = &at91_pmc_set_periph_mode;
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if (parent == NULL)
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clk->parent = &mck;
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else
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clk->parent = parent;
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for (i = 0; i < sizeof(clock_list) / sizeof(clock_list[0]); i++) {
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if (clock_list[i] == NULL) {
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clock_list[i] = clk;
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return (clk);
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}
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}
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err:
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if (clk != NULL) {
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if (clk->name != NULL)
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free(clk->name, M_PMC);
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free(clk, M_PMC);
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}
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panic("could not allocate pmc clock '%s'", name);
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return (NULL);
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}
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static void
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at91_pmc_clock_alias(const char *name, const char *alias)
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{
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struct at91_pmc_clock *clk, *alias_clk;
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clk = at91_pmc_clock_ref(name);
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if (clk)
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alias_clk = at91_pmc_clock_add(alias, 0, clk->parent);
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if (clk && alias_clk) {
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alias_clk->hz = clk->hz;
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alias_clk->pmc_mask = clk->pmc_mask;
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alias_clk->set_mode = clk->set_mode;
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}
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}
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|
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struct at91_pmc_clock *
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at91_pmc_clock_ref(const char *name)
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{
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int i;
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for (i = 0; i < sizeof(clock_list) / sizeof(clock_list[0]); i++) {
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if (clock_list[i] == NULL)
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break;
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if (strcmp(name, clock_list[i]->name) == 0)
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return (clock_list[i]);
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}
|
|
|
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//printf("at91_pmc: Warning - did not find clock '%s'", name);
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return (NULL);
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}
|
|
|
|
void
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at91_pmc_clock_deref(struct at91_pmc_clock *clk)
|
|
{
|
|
}
|
|
|
|
void
|
|
at91_pmc_clock_enable(struct at91_pmc_clock *clk)
|
|
{
|
|
/* XXX LOCKING? XXX */
|
|
if (clk->parent)
|
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at91_pmc_clock_enable(clk->parent);
|
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if (clk->refcnt++ == 0 && clk->set_mode)
|
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clk->set_mode(clk, 1);
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}
|
|
|
|
void
|
|
at91_pmc_clock_disable(struct at91_pmc_clock *clk)
|
|
{
|
|
/* XXX LOCKING? XXX */
|
|
if (--clk->refcnt == 0 && clk->set_mode)
|
|
clk->set_mode(clk, 0);
|
|
if (clk->parent)
|
|
at91_pmc_clock_disable(clk->parent);
|
|
}
|
|
|
|
static int
|
|
at91_pmc_pll_rate(struct at91_pmc_clock *clk, uint32_t reg)
|
|
{
|
|
uint32_t mul, div, freq;;
|
|
|
|
freq = clk->parent->hz;
|
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div = (reg >> clk->pll_div_shift) & clk->pll_div_mask;
|
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mul = (reg >> clk->pll_mul_shift) & clk->pll_mul_mask;
|
|
|
|
if (div != 0 && mul != 0) {
|
|
freq /= div;
|
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freq *= mul + 1;
|
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} else {
|
|
freq = 0;
|
|
}
|
|
clk->hz = freq;
|
|
return (freq);
|
|
}
|
|
|
|
static uint32_t
|
|
at91_pmc_pll_calc(struct at91_pmc_clock *clk, uint32_t out_freq)
|
|
{
|
|
uint32_t i, div = 0, mul = 0, diff = 1 << 30;
|
|
|
|
unsigned ret = 0x3e00;
|
|
|
|
if (out_freq > clk->pll_max_out)
|
|
goto fail;
|
|
|
|
for (i = 1; i < 256; i++) {
|
|
int32_t diff1;
|
|
uint32_t input, mul1;
|
|
|
|
input = clk->parent->hz / i;
|
|
if (input < clk->pll_min_in)
|
|
break;
|
|
if (input > clk->pll_max_in)
|
|
continue;
|
|
|
|
mul1 = out_freq / input;
|
|
if (mul1 > (clk->pll_mul_mask + 1))
|
|
continue;
|
|
if (mul1 == 0)
|
|
break;
|
|
|
|
diff1 = out_freq - input * mul1;
|
|
if (diff1 < 0)
|
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diff1 = -diff1;
|
|
if (diff > diff1) {
|
|
diff = diff1;
|
|
div = i;
|
|
mul = mul1;
|
|
if (diff == 0)
|
|
break;
|
|
}
|
|
}
|
|
if (diff > (out_freq >> PMC_PLL_SHIFT_TOL))
|
|
goto fail;
|
|
|
|
if (clk->set_outb != NULL)
|
|
ret |= clk->set_outb(out_freq);
|
|
|
|
return (ret |
|
|
((mul - 1) << clk->pll_mul_shift) |
|
|
(div << clk->pll_div_shift));
|
|
fail:
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
at91_pmc_init_clock(struct at91_pmc_softc *sc, unsigned int main_clock)
|
|
{
|
|
uint32_t mckr;
|
|
uint32_t mdiv;
|
|
|
|
if (at91_is_sam9()) {
|
|
uhpck.pmc_mask = PMC_SCER_UHP_SAM9;
|
|
udpck.pmc_mask = PMC_SCER_UDP_SAM9;
|
|
}
|
|
mckr = RD4(sc, PMC_MCKR);
|
|
sc->main_clock_hz = main_clock;
|
|
main_ck.hz = main_clock;
|
|
|
|
at91_pmc_pll_rate(&plla, RD4(sc, CKGR_PLLAR));
|
|
|
|
if (at91_cpu_is(AT91_CPU_SAM9G45) && (mckr & PMC_MCKR_PLLADIV2))
|
|
plla.hz /= 2;
|
|
|
|
/*
|
|
* Initialize the usb clock. This sets up pllb, but disables the
|
|
* actual clock.
|
|
*/
|
|
sc->pllb_init = at91_pmc_pll_calc(&pllb, 48000000 * 2) | 0x10000000;
|
|
at91_pmc_pll_rate(&pllb, sc->pllb_init);
|
|
|
|
#if 0
|
|
/* Turn off USB clocks */
|
|
at91_pmc_set_periph_mode(&ohci_clk, 0);
|
|
at91_pmc_set_periph_mode(&udc_clk, 0);
|
|
#endif
|
|
|
|
if (at91_is_rm92()) {
|
|
WR4(sc, PMC_SCDR, PMC_SCER_UHP | PMC_SCER_UDP);
|
|
WR4(sc, PMC_SCER, PMC_SCER_MCKUDP);
|
|
} else {
|
|
WR4(sc, PMC_SCDR, PMC_SCER_UHP_SAM9 | PMC_SCER_UDP_SAM9);
|
|
}
|
|
WR4(sc, CKGR_PLLBR, 0);
|
|
|
|
/*
|
|
* MCK and PCU derive from one of the primary clocks. Initialize
|
|
* this relationship.
|
|
*/
|
|
mck.parent = clock_list[mckr & 0x3];
|
|
mck.parent->refcnt++;
|
|
|
|
cpu.hz =
|
|
mck.hz = mck.parent->hz /
|
|
(1 << ((mckr & PMC_MCKR_PRES_MASK) >> 2));
|
|
|
|
mdiv = (mckr & PMC_MCKR_MDIV_MASK) >> 8;
|
|
if (at91_is_sam9()) {
|
|
mck.hz /= (mdiv) ? (mdiv * 2) : 1;
|
|
} else
|
|
mck.hz /= (1 + mdiv);
|
|
|
|
/* Only found on SAM9G20 */
|
|
if (at91_cpu_is(AT91_CPU_SAM9G20))
|
|
cpu.hz /= (mckr & PMC_MCKR_PDIV) ? 2 : 1;
|
|
|
|
at91_master_clock = mck.hz;
|
|
|
|
device_printf(sc->dev,
|
|
"Primary: %d Hz PLLA: %d MHz CPU: %d MHz MCK: %d MHz\n",
|
|
sc->main_clock_hz,
|
|
plla.hz / 1000000,
|
|
cpu.hz / 1000000, mck.hz / 1000000);
|
|
|
|
/* Turn off "Progamable" clocks */
|
|
WR4(sc, PMC_SCDR, PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2 |
|
|
PMC_SCER_PCK3);
|
|
|
|
/* XXX kludge, turn on all peripherals */
|
|
WR4(sc, PMC_PCER, 0xffffffff);
|
|
|
|
/* Disable all interrupts for PMC */
|
|
WR4(sc, PMC_IDR, 0xffffffff);
|
|
}
|
|
|
|
static void
|
|
at91_pmc_deactivate(device_t dev)
|
|
{
|
|
struct at91_pmc_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
bus_generic_detach(sc->dev);
|
|
if (sc->mem_res)
|
|
bus_release_resource(dev, SYS_RES_IOPORT,
|
|
rman_get_rid(sc->mem_res), sc->mem_res);
|
|
sc->mem_res = 0;
|
|
return;
|
|
}
|
|
|
|
static int
|
|
at91_pmc_activate(device_t dev)
|
|
{
|
|
struct at91_pmc_softc *sc;
|
|
int rid;
|
|
|
|
sc = device_get_softc(dev);
|
|
rid = 0;
|
|
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
RF_ACTIVE);
|
|
if (sc->mem_res == NULL)
|
|
goto errout;
|
|
return (0);
|
|
errout:
|
|
at91_pmc_deactivate(dev);
|
|
return (ENOMEM);
|
|
}
|
|
|
|
static int
|
|
at91_pmc_probe(device_t dev)
|
|
{
|
|
|
|
device_set_desc(dev, "PMC");
|
|
return (0);
|
|
}
|
|
|
|
#if !defined(AT91C_MAIN_CLOCK)
|
|
static unsigned int
|
|
at91_pmc_sense_mainf(struct at91_pmc_softc *sc)
|
|
{
|
|
unsigned int ckgr_val;
|
|
unsigned int diff, matchdiff;
|
|
int i, match;
|
|
|
|
ckgr_val = (RD4(sc, CKGR_MCFR) & CKGR_MCFR_MAINF_MASK) << 11;
|
|
|
|
/*
|
|
* Try to find the standard frequency that match best.
|
|
*/
|
|
match = 0;
|
|
matchdiff = abs(ckgr_val - at91_mainf_tbl[0]);
|
|
for (i = 1; i < MAINF_TBL_LEN; i++) {
|
|
diff = abs(ckgr_val - at91_mainf_tbl[i]);
|
|
if (diff < matchdiff) {
|
|
match = i;
|
|
matchdiff = diff;
|
|
}
|
|
}
|
|
return (at91_mainf_tbl[match]);
|
|
}
|
|
#endif
|
|
|
|
static int
|
|
at91_pmc_attach(device_t dev)
|
|
{
|
|
unsigned int mainf;
|
|
int err;
|
|
|
|
pmc_softc = device_get_softc(dev);
|
|
pmc_softc->dev = dev;
|
|
if ((err = at91_pmc_activate(dev)) != 0)
|
|
return (err);
|
|
|
|
/*
|
|
* Configure main clock frequency.
|
|
*/
|
|
#if !defined(AT91C_MAIN_CLOCK)
|
|
mainf = at91_pmc_sense_mainf(pmc_softc);
|
|
#else
|
|
mainf = AT91C_MAIN_CLOCK;
|
|
#endif
|
|
at91_pmc_init_clock(pmc_softc, mainf);
|
|
|
|
/* These clocks refrenced by "special" names */
|
|
at91_pmc_clock_alias("ohci0", "ohci_clk");
|
|
at91_pmc_clock_alias("udp0", "udp_clk");
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t at91_pmc_methods[] = {
|
|
DEVMETHOD(device_probe, at91_pmc_probe),
|
|
DEVMETHOD(device_attach, at91_pmc_attach),
|
|
{0, 0},
|
|
};
|
|
|
|
static driver_t at91_pmc_driver = {
|
|
"at91_pmc",
|
|
at91_pmc_methods,
|
|
sizeof(struct at91_pmc_softc),
|
|
};
|
|
static devclass_t at91_pmc_devclass;
|
|
|
|
DRIVER_MODULE(at91_pmc, atmelarm, at91_pmc_driver, at91_pmc_devclass, 0, 0);
|