4af12cac24
can do 64 bytes at a time and don't allocate lines in the L2 cache. These assume that everything is 64 byte aligned, and that there's more than 128 bytes of data (best for whole pages). The block load and store instructions don't follow normal memory ordering rules and require either a memory barrier or move between registers before the data can actually be used. This implementation correctly shuffles around 3 out of the 4 sets of registers in order to avoid memory barriers expect for the last 2 blocks. |
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| .. | ||
| central | ||
| compile | ||
| conf | ||
| ebus | ||
| fhc | ||
| include | ||
| isa | ||
| pci | ||
| sbus | ||
| sparc64 | ||