4b3aada9d4
The on-chip SD slots do not have PCI BARs corresponding to them, so this has to be handled in the custom SoC memory allocation. Provide memory resource for rids corresponding to BAR 0 and 1 in the custom allocation code. |
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adm5120 | ||
alchemy | ||
atheros | ||
cavium | ||
compile | ||
conf | ||
idt | ||
include | ||
malta | ||
mips | ||
nlm | ||
rmi | ||
rt305x | ||
sentry5 | ||
sibyte |