1c3bbb013d
Notable upstream commits (upstream revision in parens): - Add a JSON producer to LLDB (228636) - Don't crash on bad DWARF expression (228729) - Add support of DWARFv3 DW_OP_form_tls_address (231342) - Assembly profiler for MIPS64 (232619) - Handle FreeBSD/arm64 core files (233273) - Read/Write register for MIPS64 (233685) - Rework LLDB system initialization (233758) - SysV ABI for aarch64 (236098) - MIPS software single stepping (236696) - FreeBSD/arm live debugging support (237303) - Assembly profiler for mips32 (237420) - Parse function name from DWARF DW_AT_abstract_origin (238307) - Improve LLDB prompt handling (238313) - Add real time signals support to FreeBSDSignals (238316) - Fix race in IOHandlerProcessSTDIO (238423) - MIPS64 Branch instruction emulation for SW single stepping (238820) - Improve OSType initialization in elf object file's arch_spec (239148) - Emulation of MIPS64 floating-point branch instructions (239996) - ABI Plugin for MIPS32 (239997) - ABI Plugin for MIPS64 (240123) - MIPS32 branch emulation and single stepping (240373) - Improve instruction emulation based stack unwinding on ARM (240533) - Add branch emulation to aarch64 instruction emulator (240769)
173 lines
4.2 KiB
C++
173 lines
4.2 KiB
C++
//===-- lldb-arm64-register-enums.h -----------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef lldb_arm64_register_enums_h
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#define lldb_arm64_register_enums_h
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namespace lldb_private
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{
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// LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB)
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//---------------------------------------------------------------------------
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// Internal codes for all ARM64 registers.
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//---------------------------------------------------------------------------
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enum
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{
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k_first_gpr_arm64,
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gpr_x0_arm64 = k_first_gpr_arm64,
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gpr_x1_arm64,
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gpr_x2_arm64,
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gpr_x3_arm64,
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gpr_x4_arm64,
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gpr_x5_arm64,
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gpr_x6_arm64,
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gpr_x7_arm64,
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gpr_x8_arm64,
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gpr_x9_arm64,
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gpr_x10_arm64,
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gpr_x11_arm64,
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gpr_x12_arm64,
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gpr_x13_arm64,
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gpr_x14_arm64,
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gpr_x15_arm64,
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gpr_x16_arm64,
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gpr_x17_arm64,
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gpr_x18_arm64,
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gpr_x19_arm64,
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gpr_x20_arm64,
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gpr_x21_arm64,
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gpr_x22_arm64,
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gpr_x23_arm64,
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gpr_x24_arm64,
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gpr_x25_arm64,
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gpr_x26_arm64,
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gpr_x27_arm64,
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gpr_x28_arm64,
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gpr_fp_arm64,
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gpr_lr_arm64,
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gpr_sp_arm64,
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gpr_pc_arm64,
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gpr_cpsr_arm64,
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k_last_gpr_arm64 = gpr_cpsr_arm64,
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k_first_fpr_arm64,
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fpu_v0_arm64 = k_first_fpr_arm64,
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fpu_v1_arm64,
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fpu_v2_arm64,
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fpu_v3_arm64,
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fpu_v4_arm64,
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fpu_v5_arm64,
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fpu_v6_arm64,
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fpu_v7_arm64,
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fpu_v8_arm64,
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fpu_v9_arm64,
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fpu_v10_arm64,
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fpu_v11_arm64,
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fpu_v12_arm64,
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fpu_v13_arm64,
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fpu_v14_arm64,
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fpu_v15_arm64,
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fpu_v16_arm64,
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fpu_v17_arm64,
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fpu_v18_arm64,
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fpu_v19_arm64,
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fpu_v20_arm64,
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fpu_v21_arm64,
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fpu_v22_arm64,
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fpu_v23_arm64,
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fpu_v24_arm64,
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fpu_v25_arm64,
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fpu_v26_arm64,
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fpu_v27_arm64,
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fpu_v28_arm64,
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fpu_v29_arm64,
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fpu_v30_arm64,
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fpu_v31_arm64,
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fpu_fpsr_arm64,
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fpu_fpcr_arm64,
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k_last_fpr_arm64 = fpu_fpcr_arm64,
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exc_far_arm64,
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exc_esr_arm64,
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exc_exception_arm64,
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dbg_bvr0_arm64,
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dbg_bvr1_arm64,
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dbg_bvr2_arm64,
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dbg_bvr3_arm64,
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dbg_bvr4_arm64,
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dbg_bvr5_arm64,
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dbg_bvr6_arm64,
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dbg_bvr7_arm64,
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dbg_bvr8_arm64,
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dbg_bvr9_arm64,
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dbg_bvr10_arm64,
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dbg_bvr11_arm64,
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dbg_bvr12_arm64,
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dbg_bvr13_arm64,
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dbg_bvr14_arm64,
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dbg_bvr15_arm64,
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dbg_bcr0_arm64,
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dbg_bcr1_arm64,
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dbg_bcr2_arm64,
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dbg_bcr3_arm64,
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dbg_bcr4_arm64,
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dbg_bcr5_arm64,
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dbg_bcr6_arm64,
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dbg_bcr7_arm64,
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dbg_bcr8_arm64,
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dbg_bcr9_arm64,
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dbg_bcr10_arm64,
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dbg_bcr11_arm64,
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dbg_bcr12_arm64,
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dbg_bcr13_arm64,
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dbg_bcr14_arm64,
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dbg_bcr15_arm64,
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dbg_wvr0_arm64,
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dbg_wvr1_arm64,
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dbg_wvr2_arm64,
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dbg_wvr3_arm64,
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dbg_wvr4_arm64,
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dbg_wvr5_arm64,
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dbg_wvr6_arm64,
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dbg_wvr7_arm64,
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dbg_wvr8_arm64,
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dbg_wvr9_arm64,
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dbg_wvr10_arm64,
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dbg_wvr11_arm64,
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dbg_wvr12_arm64,
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dbg_wvr13_arm64,
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dbg_wvr14_arm64,
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dbg_wvr15_arm64,
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dbg_wcr0_arm64,
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dbg_wcr1_arm64,
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dbg_wcr2_arm64,
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dbg_wcr3_arm64,
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dbg_wcr4_arm64,
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dbg_wcr5_arm64,
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dbg_wcr6_arm64,
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dbg_wcr7_arm64,
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dbg_wcr8_arm64,
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dbg_wcr9_arm64,
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dbg_wcr10_arm64,
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dbg_wcr11_arm64,
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dbg_wcr12_arm64,
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dbg_wcr13_arm64,
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dbg_wcr14_arm64,
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dbg_wcr15_arm64,
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k_num_registers_arm64,
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k_num_gpr_registers_arm64 = k_last_gpr_arm64 - k_first_gpr_arm64 + 1,
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k_num_fpr_registers_arm64 = k_last_fpr_arm64 - k_first_fpr_arm64 + 1
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};
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}
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#endif // #ifndef lldb_arm64_register_enums_h
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