4c024bbdf8
supports All Cyrix CPUs, IBM Blue Lightning CPU and NexGen (now AMD)
Nx586 CPU, and initialize special registers of Cyrix CPU and msr of
IBM Blue Lightning CPU.
If revision of Cyrix 6x86 CPU < 2.7, CPU cache is enabled in
write-through mode. This can be disabled by kernel configuration
options.
Reviewed by: Bruce Evans <bde@freebsd.org> and
Jordan K. Hubbard <jkh@freebsd.org>
277 lines
9.1 KiB
C
277 lines
9.1 KiB
C
/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
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* $Id: specialreg.h,v 1.12 1997/02/22 09:35:15 peter Exp $
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*/
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#ifndef _MACHINE_SPECIALREG_H_
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#define _MACHINE_SPECIALREG_H_
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/*
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* Bits in 386 special registers:
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*/
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#define CR0_PE 0x00000001 /* Protected mode Enable */
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#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
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#ifdef notused
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#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
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#endif
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#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
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#ifdef notused
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#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
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#endif
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#define CR0_PG 0x80000000 /* PaGing enable */
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/*
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* Bits in 486 special registers:
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*/
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#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
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#define CR0_WP 0x00010000 /* Write Protect (honor page protect in
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all modes) */
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#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
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#define CR0_NW 0x20000000 /* Not Write-through */
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#define CR0_CD 0x40000000 /* Cache Disable */
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/*
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* Bits in PPro special registers
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*/
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#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
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#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
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#define CR4_TSD 0x00000004 /* Time stamp disable */
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#define CR4_DE 0x00000008 /* Debugging extensions */
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#define CR4_PSE 0x00000010 /* Page size extensions */
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#define CR4_PAE 0x00000020 /* Physical address extension */
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#define CR4_MCE 0x00000040 /* Machine check enable */
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#define CR4_PGE 0x00000080 /* Page global enable */
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#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
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/*
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* CPUID instruction features register
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*/
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#define CPUID_FPU 0x0001
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#define CPUID_VME 0x0002
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#define CPUID_DE 0x0004
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#define CPUID_PSE 0x0008
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#define CPUID_TSC 0x0010
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#define CPUID_MSR 0x0020
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#define CPUID_PAE 0x0040
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#define CPUID_MCE 0x0080
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#define CPUID_CX8 0x0100
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#define CPUID_APIC 0x0200
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#define CPUID_B10 0x0400
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#define CPUID_B11 0x0800
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#define CPUID_MTRR 0x1000
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#define CPUID_PGE 0x2000
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#define CPUID_MCA 0x4000
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#define CPUID_CMOV 0x8000
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/*
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* Cyrix configuration registers, accessible as IO ports.
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*/
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#define CCR0 0xc0 /* Configuration control register 0 */
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#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
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non-cacheable */
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#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
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#define CCR0_A20M 0x04 /* Enables A20M# input pin */
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#define CCR0_KEN 0x08 /* Enables KEN# input pin */
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#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
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#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
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state */
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#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
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assoc */
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#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
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#define CCR1 0xc1 /* Configuration control register 1 */
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#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
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#define CCR1_SMI 0x02 /* Enables SMM pins */
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#define CCR1_SMAC 0x04 /* System management memory access */
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#define CCR1_MMAC 0x08 /* Main memory access */
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#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
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#define CCR1_SM3 0x80 /* SMM address space address region 3 */
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#define CCR2 0xc2
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#define CCR2_WB 0x02 /* Enables WB cache interface pins */
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#define CCR2_SADS 0x02 /* Slow ADS */
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#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
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#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
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#define CCR2_WT1 0x10 /* WT region 1 */
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#define CCR2_WPR1 0x10 /* Write-protect region 1 */
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#define CCR2_BARB 0x20 /* Flushes write-back cache when entering
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hold state. */
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#define CCR2_BWRT 0x40 /* Enables burst write cycles */
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#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
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#define CCR3 0xc3
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#define CCR3_SMILOCK 0x01 /* SMM register lock */
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#define CCR3_NMI 0x02 /* Enables NMI during SMM */
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#define CCR3_LINBRST 0x04 /* Linear address burst cycles */
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#define CCR3_SMMMODE 0x08 /* SMM Mode */
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#define CCR3_MAPEN0 0x10 /* Enables Map0 */
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#define CCR3_MAPEN1 0x20 /* Enables Map1 */
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#define CCR3_MAPEN2 0x40 /* Enables Map2 */
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#define CCR3_MAPEN3 0x80 /* Enables Map3 */
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#define CCR4 0xe8
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#define CCR4_IOMASK 0x07
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#define CCR4_MEM 0x08 /* Enables momory bypassing */
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#define CCR4_DTE 0x10 /* Enables directory table entry cache */
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#define CCR4_FASTFPE 0x20 /* Fast FPU exception */
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#define CCR4_CPUID 0x80 /* Enables CPUID instruction */
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#define CCR5 0xe9
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#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
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#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
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#define CCR5_LBR1 0x10 /* Local bus region 1 */
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#define CCR5_ARREN 0x20 /* Enables ARR region */
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/* Performance Control Register (5x86 only). */
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#define PCR0 0x20
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#define PCR0_RSTK 0x01 /* Enables return stack */
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#define PCR0_BTB 0x02 /* Enables branch target buffer */
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#define PCR0_LOOP 0x04 /* Enables loop */
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#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
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serialize pipe. */
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#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
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#define PCR0_BTBRT 0x40 /* Enables BTB test register. */
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#define PCR0_LSSER 0x80 /* Disable reorder */
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/* Device Identification Registers */
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#define DIR0 0xfe
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#define DIR1 0xff
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/*
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* The following four 3-byte registers control the non-cacheable regions.
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* These registers must be written as three separate bytes.
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*
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* NCRx+0: A31-A24 of starting address
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* NCRx+1: A23-A16 of starting address
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* NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
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*
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* The non-cacheable region's starting address must be aligned to the
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* size indicated by the NCR_SIZE_xx field.
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*/
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#define NCR1 0xc4
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#define NCR2 0xc7
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#define NCR3 0xca
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#define NCR4 0xcd
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#define NCR_SIZE_0K 0
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#define NCR_SIZE_4K 1
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#define NCR_SIZE_8K 2
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#define NCR_SIZE_16K 3
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#define NCR_SIZE_32K 4
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#define NCR_SIZE_64K 5
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#define NCR_SIZE_128K 6
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#define NCR_SIZE_256K 7
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#define NCR_SIZE_512K 8
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#define NCR_SIZE_1M 9
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#define NCR_SIZE_2M 10
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#define NCR_SIZE_4M 11
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#define NCR_SIZE_8M 12
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#define NCR_SIZE_16M 13
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#define NCR_SIZE_32M 14
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#define NCR_SIZE_4G 15
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/*
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* The address region registers are used to specify the location and
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* size for the eight address regions.
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*
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* ARRx + 0: A31-A24 of start address
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* ARRx + 1: A23-A16 of start address
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* ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
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*/
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#define ARR0 0xc4
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#define ARR1 0xc7
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#define ARR2 0xca
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#define ARR3 0xcd
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#define ARR4 0xd0
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#define ARR5 0xd3
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#define ARR6 0xd6
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#define ARR7 0xd9
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#define ARR_SIZE_0K 0
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#define ARR_SIZE_4K 1
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#define ARR_SIZE_8K 2
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#define ARR_SIZE_16K 3
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#define ARR_SIZE_32K 4
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#define ARR_SIZE_64K 5
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#define ARR_SIZE_128K 6
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#define ARR_SIZE_256K 7
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#define ARR_SIZE_512K 8
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#define ARR_SIZE_1M 9
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#define ARR_SIZE_2M 10
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#define ARR_SIZE_4M 11
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#define ARR_SIZE_8M 12
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#define ARR_SIZE_16M 13
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#define ARR_SIZE_32M 14
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#define ARR_SIZE_4G 15
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/*
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* The region control registers specify the attributes associated with
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* the ARRx addres regions.
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*/
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#define RCR0 0xdc
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#define RCR1 0xdd
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#define RCR2 0xde
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#define RCR3 0xdf
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#define RCR4 0xe0
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#define RCR5 0xe1
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#define RCR6 0xe2
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#define RCR7 0xe3
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#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
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#define RCR_RCE 0x01 /* Enables caching for ARR7. */
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#define RCR_WWO 0x02 /* Weak write ordering. */
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#define RCR_WL 0x04 /* Weak locking. */
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#define RCR_WG 0x08 /* Write gathering. */
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#define RCR_WT 0x10 /* Write-through. */
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#define RCR_NLB 0x20 /* LBA# pin is not asserted. */
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#ifndef LOCORE
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static __inline u_char
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read_cyrix_reg(u_char reg)
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{
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outb(0x22, reg);
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return inb(0x23);
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}
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static __inline void
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write_cyrix_reg(u_char reg, u_char data)
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{
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outb(0x22, reg);
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outb(0x23, data);
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}
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#endif
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#endif /* !_MACHINE_SPECIALREG_H_ */
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