c4df93502d
This is untested but should at least allow an AR724X to boot. The current code is lacking the detail needed to expose the PCIe bus. It is also lacking any NIC, PLL or flush/WB code.
166 lines
4.1 KiB
C
166 lines
4.1 KiB
C
/*-
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* Copyright (c) 2010 Adrian Chadd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <machine/cpuregs.h>
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#include <mips/sentry5/s5reg.h>
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cons.h>
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#include <sys/kdb.h>
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#include <sys/reboot.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#include <net/ethernet.h>
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#include <machine/clock.h>
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#include <machine/cpu.h>
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#include <machine/hwfunc.h>
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#include <machine/md_var.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#include <mips/atheros/ar71xxreg.h>
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#include <mips/atheros/ar724xreg.h>
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#include <mips/atheros/ar71xx_cpudef.h>
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#include <mips/atheros/ar724x_chip.h>
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static void
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ar724x_chip_detect_mem_size(void)
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{
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}
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static void
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ar724x_chip_detect_sys_frequency(void)
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{
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uint32_t pll;
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uint32_t freq;
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uint32_t div;
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pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
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freq = div * AR724X_BASE_FREQ;
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div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
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freq *= div;
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u_ar71xx_cpu_freq = freq;
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div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
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u_ar71xx_ddr_freq = freq / div;
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div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
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u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
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}
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static void
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ar724x_chip_device_stop(uint32_t mask)
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{
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uint32_t mask_inv, reg;
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mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
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reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
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reg |= mask;
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reg &= ~mask_inv;
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ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
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}
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static void
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ar724x_chip_device_start(uint32_t mask)
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{
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uint32_t mask_inv, reg;
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mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
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reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
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reg &= ~mask;
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reg |= mask_inv;
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ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
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}
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static int
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ar724x_chip_device_stopped(uint32_t mask)
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{
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uint32_t reg;
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reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
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return ((reg & mask) == mask);
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}
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static void
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ar724x_chip_set_pll_ge0(int speed)
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{
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}
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static void
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ar724x_chip_set_pll_ge1(int speed)
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{
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}
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static void
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ar724x_chip_ddr_flush_ge0(void)
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{
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}
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static void
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ar724x_chip_ddr_flush_ge1(void)
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{
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}
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static uint32_t
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ar724x_chip_get_eth_pll(unsigned int mac, int speed)
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{
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return 0;
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}
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struct ar71xx_cpu_def ar724x_chip_def = {
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&ar724x_chip_detect_mem_size,
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&ar724x_chip_detect_sys_frequency,
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&ar724x_chip_device_stop,
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&ar724x_chip_device_start,
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&ar724x_chip_device_stopped,
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&ar724x_chip_set_pll_ge0,
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&ar724x_chip_set_pll_ge1,
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&ar724x_chip_ddr_flush_ge0,
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&ar724x_chip_ddr_flush_ge1,
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&ar724x_chip_get_eth_pll,
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NULL, /* ar71xx_chip_irq_flush_ip2 */
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NULL /* ar71xx_chip_init_usb_peripheral */
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};
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