8dee0fd04c
r235162: Initial LPC32x0 support. Includes DTS file for Embedded Artists EA3250 board. Peripherals currently supported: - Serial ports - Interrupt controller - Timers - Ethernet - USB host - Framebuffer (in conjunction with SSD1289 LCD controller) - RTC - SPI - GPIO Submitted by: Jakub Wojciech Klama <jceel@freebsd.org>
321 lines
8.7 KiB
C
321 lines
8.7 KiB
C
/*-
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* Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timetc.h>
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#include <sys/timeet.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/frame.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/lpc/lpcreg.h>
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#include <arm/lpc/lpcvar.h>
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struct lpc_timer_softc {
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device_t lt_dev;
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struct eventtimer lt_et;
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struct resource * lt_res[5];
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bus_space_tag_t lt_bst0;
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bus_space_handle_t lt_bsh0;
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bus_space_tag_t lt_bst1;
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bus_space_handle_t lt_bsh1;
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int lt_oneshot;
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uint32_t lt_period;
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};
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static struct resource_spec lpc_timer_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 1, RF_ACTIVE },
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{ -1, 0 }
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};
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static struct lpc_timer_softc *timer_softc = NULL;
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static int lpc_timer_initialized = 0;
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static int lpc_timer_probe(device_t);
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static int lpc_timer_attach(device_t);
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static int lpc_timer_start(struct eventtimer *, struct bintime *first,
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struct bintime *);
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static int lpc_timer_stop(struct eventtimer *et);
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static unsigned lpc_get_timecount(struct timecounter *);
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static int lpc_hardclock(void *);
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#define timer0_read_4(sc, reg) \
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bus_space_read_4(sc->lt_bst0, sc->lt_bsh0, reg)
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#define timer0_write_4(sc, reg, val) \
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bus_space_write_4(sc->lt_bst0, sc->lt_bsh0, reg, val)
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#define timer0_clear(sc) \
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do { \
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timer0_write_4(sc, LPC_TIMER_TC, 0); \
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timer0_write_4(sc, LPC_TIMER_PR, 0); \
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timer0_write_4(sc, LPC_TIMER_PC, 0); \
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} while(0)
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#define timer1_read_4(sc, reg) \
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bus_space_read_4(sc->lt_bst1, sc->lt_bsh1, reg)
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#define timer1_write_4(sc, reg, val) \
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bus_space_write_4(sc->lt_bst1, sc->lt_bsh1, reg, val)
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#define timer1_clear(sc) \
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do { \
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timer1_write_4(sc, LPC_TIMER_TC, 0); \
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timer1_write_4(sc, LPC_TIMER_PR, 0); \
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timer1_write_4(sc, LPC_TIMER_PC, 0); \
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} while(0)
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static struct timecounter lpc_timecounter = {
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.tc_get_timecount = lpc_get_timecount,
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.tc_name = "LPC32x0 Timer1",
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.tc_frequency = 0, /* will be filled later */
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.tc_counter_mask = ~0u,
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.tc_quality = 1000,
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};
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static int
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lpc_timer_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "lpc,timer"))
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return (ENXIO);
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device_set_desc(dev, "LPC32x0 timer");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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lpc_timer_attach(device_t dev)
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{
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void *intrcookie;
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struct lpc_timer_softc *sc = device_get_softc(dev);
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phandle_t node;
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uint32_t freq;
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if (timer_softc)
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return (ENXIO);
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timer_softc = sc;
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if (bus_alloc_resources(dev, lpc_timer_spec, sc->lt_res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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sc->lt_bst0 = rman_get_bustag(sc->lt_res[0]);
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sc->lt_bsh0 = rman_get_bushandle(sc->lt_res[0]);
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sc->lt_bst1 = rman_get_bustag(sc->lt_res[1]);
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sc->lt_bsh1 = rman_get_bushandle(sc->lt_res[1]);
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if (bus_setup_intr(dev, sc->lt_res[2], INTR_TYPE_CLK,
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lpc_hardclock, NULL, sc, &intrcookie)) {
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device_printf(dev, "could not setup interrupt handler\n");
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bus_release_resources(dev, lpc_timer_spec, sc->lt_res);
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return (ENXIO);
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}
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/* Enable timer clock */
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lpc_pwr_write(dev, LPC_CLKPWR_TIMCLK_CTRL1,
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LPC_CLKPWR_TIMCLK_CTRL1_TIMER0 |
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LPC_CLKPWR_TIMCLK_CTRL1_TIMER1);
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/* Get PERIPH_CLK encoded in parent bus 'bus-frequency' property */
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node = ofw_bus_get_node(dev);
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if (OF_getprop(OF_parent(node), "bus-frequency", &freq,
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sizeof(pcell_t)) <= 0) {
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bus_release_resources(dev, lpc_timer_spec, sc->lt_res);
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bus_teardown_intr(dev, sc->lt_res[2], intrcookie);
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device_printf(dev, "could not obtain base clock frequency\n");
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return (ENXIO);
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}
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freq = fdt32_to_cpu(freq);
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/* Set desired frequency in event timer and timecounter */
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sc->lt_et.et_frequency = (uint64_t)freq;
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lpc_timecounter.tc_frequency = (uint64_t)freq;
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sc->lt_et.et_name = "LPC32x0 Timer0";
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sc->lt_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
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sc->lt_et.et_quality = 1000;
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sc->lt_et.et_min_period.sec = 0;
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sc->lt_et.et_min_period.frac =
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((0x00000002LLU << 32) / sc->lt_et.et_frequency) << 32;
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sc->lt_et.et_max_period.sec = 0xfffffff0U / sc->lt_et.et_frequency;
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sc->lt_et.et_max_period.frac =
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((0xfffffffeLLU << 32) / sc->lt_et.et_frequency) << 32;
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sc->lt_et.et_start = lpc_timer_start;
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sc->lt_et.et_stop = lpc_timer_stop;
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sc->lt_et.et_priv = sc;
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et_register(&sc->lt_et);
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tc_init(&lpc_timecounter);
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/* Reset and enable timecounter */
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timer1_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_RESET);
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timer1_write_4(sc, LPC_TIMER_TCR, 0);
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timer1_clear(sc);
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timer1_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE);
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/* DELAY() now can work properly */
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lpc_timer_initialized = 1;
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return (0);
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}
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static int
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lpc_timer_start(struct eventtimer *et, struct bintime *first,
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struct bintime *period)
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{
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struct lpc_timer_softc *sc = (struct lpc_timer_softc *)et->et_priv;
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uint32_t ticks;
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if (period == NULL)
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sc->lt_oneshot = 1;
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else {
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sc->lt_oneshot = 0;
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sc->lt_period = (sc->lt_et.et_frequency * (first->frac >> 32)) >> 32;
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sc->lt_period += sc->lt_et.et_frequency * first->sec;
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}
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if (first == NULL)
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ticks = sc->lt_period;
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else {
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ticks = (sc->lt_et.et_frequency * (first->frac >> 32)) >> 32;
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if (first->sec != 0)
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ticks += sc->lt_et.et_frequency * first->sec;
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}
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/* Reset timer */
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timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_RESET);
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timer0_write_4(sc, LPC_TIMER_TCR, 0);
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/* Start timer */
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timer0_clear(sc);
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timer0_write_4(sc, LPC_TIMER_MR0, ticks);
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timer0_write_4(sc, LPC_TIMER_MCR, LPC_TIMER_MCR_MR0I | LPC_TIMER_MCR_MR0S);
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timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE);
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return (0);
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}
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static int
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lpc_timer_stop(struct eventtimer *et)
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{
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struct lpc_timer_softc *sc = (struct lpc_timer_softc *)et->et_priv;
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timer0_write_4(sc, LPC_TIMER_TCR, 0);
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return (0);
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}
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static device_method_t lpc_timer_methods[] = {
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DEVMETHOD(device_probe, lpc_timer_probe),
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DEVMETHOD(device_attach, lpc_timer_attach),
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{ 0, 0 }
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};
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static driver_t lpc_timer_driver = {
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"timer",
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lpc_timer_methods,
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sizeof(struct lpc_timer_softc),
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};
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static devclass_t lpc_timer_devclass;
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DRIVER_MODULE(timer, simplebus, lpc_timer_driver, lpc_timer_devclass, 0, 0);
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static int
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lpc_hardclock(void *arg)
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{
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struct lpc_timer_softc *sc = (struct lpc_timer_softc *)arg;
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/* Reset pending interrupt */
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timer0_write_4(sc, LPC_TIMER_IR, 0xffffffff);
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/* Start timer again */
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if (!sc->lt_oneshot) {
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timer0_clear(sc);
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timer0_write_4(sc, LPC_TIMER_MR0, sc->lt_period);
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timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE);
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}
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if (sc->lt_et.et_active)
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sc->lt_et.et_event_cb(&sc->lt_et, sc->lt_et.et_arg);
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return (FILTER_HANDLED);
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}
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static unsigned
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lpc_get_timecount(struct timecounter *tc)
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{
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return timer1_read_4(timer_softc, LPC_TIMER_TC);
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}
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void
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cpu_initclocks(void)
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{
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cpu_initclocks_bsp();
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}
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void
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DELAY(int usec)
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{
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uint32_t counter;
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uint32_t first, last;
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int val = (lpc_timecounter.tc_frequency / 1000000 + 1) * usec;
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/* Timer is not initialized yet */
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if (!lpc_timer_initialized) {
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for (; usec > 0; usec--)
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for (counter = 100; counter > 0; counter--)
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;
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return;
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}
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first = lpc_get_timecount(&lpc_timecounter);
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while (val > 0) {
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last = lpc_get_timecount(&lpc_timecounter);
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if (last < first) {
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/* Timer rolled over */
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last = first;
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}
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val -= (last - first);
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first = last;
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}
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}
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