27d5dc189c
It improves on sio(4) in the following areas: o Fully newbusified to allow for memory mapped I/O. This is a must for ia64 and sparc64, o Machine dependent code to take full advantage of machine and firm- ware specific ways to define serial consoles and/or debug ports. o Hardware abstraction layer to allow the driver to be used with various UARTs, such as the well-known ns8250 family of UARTs, the Siemens sab82532 or the Zilog Z8530. This is especially important for pc98 and sparc64 where it's common to have different UARTs, o The notion of system devices to unkludge low-level consoles and remote gdb ports and provides the mechanics necessary to support the keyboard on sparc64 (which is UART based). o The notion of a kernel interface so that a UART can be tied to something other than the well-known TTY interface. This is needed on sparc64 to present the user with a device and ioctl handling suitable for a keyboard, but also allows us to cleanly hide an UART when used as a debug port. Following is a list of features and bugs/flaws specific to the ns8250 family of UARTs as compared to their support in sio(4): o The uart(4) driver determines the FIFO size and automaticly takes advantages of larger FIFOs and/or additional features. Note that since I don't have sufficient access to 16[679]5x UARTs, hardware flow control has not been enabled. This is almost trivial to do, provided one can test. The downside of this is that broken UARTs are more likely to not work correctly with uart(4). The need for tunables or knobs may be large enough to warrant their creation. o The uart(4) driver does not share the same bumpy history as sio(4) and will therefore not provide the necessary hooks, tweaks, quirks or work-arounds to deal with once common hardware. To that extend, uart(4) supports a subset of the UARTs that sio(4) supports. The question before us is whether the subset is sufficient for current hardware. o There is no support for multiport UARTs in uart(4). The decision behind this is that uart(4) deals with one EIA RS232-C interface. Packaging of multiple interfaces in a single chip or on a single expansion board is beyond the scope of uart(4) and is now mostly left for puc(4) to deal with. Lack of hardware made it impossible to actually implement such a dependency other than is present for the dual channel SAB82532 and Z8350 SCCs. The current list of missing features is: o No configuration capabilities. A set of tunables and sysctls is being worked out. There are likely not going to be any or much compile-time knobs. Such configuration does not fit well with current hardware. o No support for the PPS API. This is partly dependent on the ability to configure uart(4) and partly dependent on having sufficient information to implement it properly. As usual, the manpage is present but lacks the attention the software has gotten.
83 lines
2.9 KiB
C
83 lines
2.9 KiB
C
/*
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* Copyright (c) 2003 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_UART_H_
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#define _DEV_UART_H_
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/*
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* Bus access structure. This structure holds the minimum information needed
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* to access the UART. The rclk field, although not important to actually
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* access the UART, is important for baudrate programming, delay loops and
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* other timing related computations.
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*/
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struct uart_bas {
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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u_int regshft;
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u_int rclk;
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};
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#define uart_regofs(bas, reg) ((reg) << (bas)->regshft)
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#define uart_getreg(bas, reg) \
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bus_space_read_1((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
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#define uart_setreg(bas, reg, value) \
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bus_space_write_1((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
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/* 16-bit I/O (e.g. to divisor latch) */
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#define uart_getdreg(bas, reg) \
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bus_space_read_2((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
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#define uart_setdreg(bas, reg, value) \
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bus_space_write_2((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
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/*
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* XXX we don't know the length of the bus space address range in use by
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* the UART. Since barriers don't use the length field currently, we put
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* a zero there for now.
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*/
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#define uart_barrier(bas) \
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bus_space_barrier((bas)->bst, (bas)->bsh, 0, 0, \
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BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
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/*
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* Device flags.
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*/
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#define UART_FLAGS_CONSOLE(f) ((f) & 0x10)
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#define UART_FLAGS_DBGPORT(f) ((f) & 0x80)
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/*
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* Data parity values (magical numbers related to ns8250).
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*/
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#define UART_PARITY_NONE 0
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#define UART_PARITY_ODD 1
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#define UART_PARITY_EVEN 3
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#define UART_PARITY_MARK 5
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#define UART_PARITY_SPACE 7
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#endif /* _DEV_UART_H_ */
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