4d83500fda
This fixes system hangs on reading device registers on aarch64. Tested with: Marvell MACCHIATObin (Armada8k) + mlx4en, amdgpu Submitted by: Greg V <greg@unrelenting.technology> Differential Revision: https://reviews.freebsd.org/D20789 MFC after: 1 week Sponsored by: Mellanox Technologies
482 lines
10 KiB
C
482 lines
10 KiB
C
/*-
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* Copyright (c) 2010 Isilon Systems, Inc.
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* Copyright (c) 2010 iX Systems, Inc.
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* Copyright (c) 2010 Panasas, Inc.
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* Copyright (c) 2013-2015 Mellanox Technologies, Ltd.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _LINUX_IO_H_
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#define _LINUX_IO_H_
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#include <machine/vm.h>
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#include <sys/endian.h>
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#include <sys/types.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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/*
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* XXX This is all x86 specific. It should be bus space access.
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*/
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/* rmb and wmb are declared in machine/atomic.h, so should be included first. */
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#ifndef __io_br
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#define __io_br() __compiler_membar()
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#endif
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#ifndef __io_ar
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#ifdef rmb
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#define __io_ar() rmb()
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#else
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#define __io_ar() __compiler_membar()
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#endif
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#endif
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#ifndef __io_bw
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#ifdef wmb
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#define __io_bw() wmb()
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#else
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#define __io_bw() __compiler_membar()
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#endif
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#endif
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#ifndef __io_aw
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#define __io_aw() __compiler_membar()
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#endif
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/* Access MMIO registers atomically without barriers and byte swapping. */
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static inline uint8_t
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__raw_readb(const volatile void *addr)
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{
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return (*(const volatile uint8_t *)addr);
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}
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#define __raw_readb(addr) __raw_readb(addr)
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static inline void
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__raw_writeb(uint8_t v, volatile void *addr)
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{
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*(volatile uint8_t *)addr = v;
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}
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#define __raw_writeb(v, addr) __raw_writeb(v, addr)
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static inline uint16_t
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__raw_readw(const volatile void *addr)
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{
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return (*(const volatile uint16_t *)addr);
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}
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#define __raw_readw(addr) __raw_readw(addr)
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static inline void
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__raw_writew(uint16_t v, volatile void *addr)
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{
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*(volatile uint16_t *)addr = v;
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}
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#define __raw_writew(v, addr) __raw_writew(v, addr)
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static inline uint32_t
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__raw_readl(const volatile void *addr)
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{
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return (*(const volatile uint32_t *)addr);
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}
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#define __raw_readl(addr) __raw_readl(addr)
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static inline void
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__raw_writel(uint32_t v, volatile void *addr)
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{
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*(volatile uint32_t *)addr = v;
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}
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#define __raw_writel(v, addr) __raw_writel(v, addr)
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#ifdef __LP64__
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static inline uint64_t
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__raw_readq(const volatile void *addr)
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{
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return (*(const volatile uint64_t *)addr);
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}
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#define __raw_readq(addr) __raw_readq(addr)
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static inline void
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__raw_writeq(uint64_t v, volatile void *addr)
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{
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*(volatile uint64_t *)addr = v;
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}
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#define __raw_writeq(v, addr) __raw_writeq(v, addr)
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#endif
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#define mmiowb() barrier()
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/* Access little-endian MMIO registers atomically with memory barriers. */
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#undef readb
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static inline uint8_t
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readb(const volatile void *addr)
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{
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uint8_t v;
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__io_br();
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v = *(const volatile uint8_t *)addr;
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__io_ar();
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return (v);
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}
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#define readb(addr) readb(addr)
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#undef writeb
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static inline void
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writeb(uint8_t v, volatile void *addr)
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{
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__io_bw();
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*(volatile uint8_t *)addr = v;
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__io_aw();
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}
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#define writeb(v, addr) writeb(v, addr)
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#undef readw
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static inline uint16_t
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readw(const volatile void *addr)
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{
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uint16_t v;
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__io_br();
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v = le16toh(__raw_readw(addr));
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__io_ar();
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return (v);
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}
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#define readw(addr) readw(addr)
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#undef writew
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static inline void
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writew(uint16_t v, volatile void *addr)
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{
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__io_bw();
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__raw_writew(htole16(v), addr);
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__io_aw();
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}
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#define writew(v, addr) writew(v, addr)
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#undef readl
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static inline uint32_t
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readl(const volatile void *addr)
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{
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uint32_t v;
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__io_br();
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v = le32toh(__raw_readl(addr));
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__io_ar();
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return (v);
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}
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#define readl(addr) readl(addr)
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#undef writel
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static inline void
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writel(uint32_t v, volatile void *addr)
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{
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__io_bw();
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__raw_writel(htole32(v), addr);
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__io_aw();
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}
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#define writel(v, addr) writel(v, addr)
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#undef readq
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#undef writeq
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#ifdef __LP64__
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static inline uint64_t
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readq(const volatile void *addr)
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{
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uint64_t v;
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__io_br();
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v = le64toh(__raw_readq(addr));
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__io_ar();
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return (v);
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}
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#define readq(addr) readq(addr)
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static inline void
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writeq(uint64_t v, volatile void *addr)
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{
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__io_bw();
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__raw_writeq(htole64(v), addr);
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__io_aw();
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}
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#define writeq(v, addr) writeq(v, addr)
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#endif
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/* Access little-endian MMIO registers atomically without memory barriers. */
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#undef readb_relaxed
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static inline uint8_t
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readb_relaxed(const volatile void *addr)
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{
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return (__raw_readb(addr));
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}
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#define readb_relaxed(addr) readb_relaxed(addr)
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#undef writeb_relaxed
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static inline void
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writeb_relaxed(uint8_t v, volatile void *addr)
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{
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__raw_writeb(v, addr);
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}
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#define writeb_relaxed(v, addr) writeb_relaxed(v, addr)
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#undef readw_relaxed
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static inline uint16_t
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readw_relaxed(const volatile void *addr)
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{
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return (le16toh(__raw_readw(addr)));
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}
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#define readw_relaxed(addr) readw_relaxed(addr)
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#undef writew_relaxed
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static inline void
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writew_relaxed(uint16_t v, volatile void *addr)
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{
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__raw_writew(htole16(v), addr);
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}
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#define writew_relaxed(v, addr) writew_relaxed(v, addr)
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#undef readl_relaxed
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static inline uint32_t
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readl_relaxed(const volatile void *addr)
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{
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return (le32toh(__raw_readl(addr)));
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}
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#define readl_relaxed(addr) readl_relaxed(addr)
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#undef writel_relaxed
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static inline void
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writel_relaxed(uint32_t v, volatile void *addr)
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{
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__raw_writel(htole32(v), addr);
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}
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#define writel_relaxed(v, addr) writel_relaxed(v, addr)
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#undef readq_relaxed
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#undef writeq_relaxed
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#ifdef __LP64__
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static inline uint64_t
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readq_relaxed(const volatile void *addr)
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{
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return (le64toh(__raw_readq(addr)));
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}
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#define readq_relaxed(addr) readq_relaxed(addr)
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static inline void
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writeq_relaxed(uint64_t v, volatile void *addr)
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{
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__raw_writeq(htole64(v), addr);
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}
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#define writeq_relaxed(v, addr) writeq_relaxed(v, addr)
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#endif
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/* XXX On Linux ioread and iowrite handle both MMIO and port IO. */
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#undef ioread8
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static inline uint8_t
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ioread8(const volatile void *addr)
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{
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return (readb(addr));
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}
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#define ioread8(addr) ioread8(addr)
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#undef ioread16
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static inline uint16_t
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ioread16(const volatile void *addr)
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{
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return (readw(addr));
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}
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#define ioread16(addr) ioread16(addr)
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#undef ioread16be
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static inline uint16_t
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ioread16be(const volatile void *addr)
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{
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uint16_t v;
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__io_br();
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v = (be16toh(__raw_readw(addr)));
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__io_ar();
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return (v);
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}
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#define ioread16be(addr) ioread16be(addr)
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#undef ioread32
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static inline uint32_t
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ioread32(const volatile void *addr)
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{
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return (readl(addr));
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}
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#define ioread32(addr) ioread32(addr)
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#undef ioread32be
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static inline uint32_t
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ioread32be(const volatile void *addr)
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{
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uint32_t v;
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__io_br();
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v = (be32toh(__raw_readl(addr)));
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__io_ar();
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return (v);
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}
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#define ioread32be(addr) ioread32be(addr)
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#undef iowrite8
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static inline void
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iowrite8(uint8_t v, volatile void *addr)
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{
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writeb(v, addr);
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}
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#define iowrite8(v, addr) iowrite8(v, addr)
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#undef iowrite16
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static inline void
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iowrite16(uint16_t v, volatile void *addr)
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{
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writew(v, addr);
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}
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#define iowrite16 iowrite16
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#undef iowrite32
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static inline void
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iowrite32(uint32_t v, volatile void *addr)
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{
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writel(v, addr);
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}
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#define iowrite32(v, addr) iowrite32(v, addr)
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#undef iowrite32be
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static inline void
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iowrite32be(uint32_t v, volatile void *addr)
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{
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__io_bw();
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__raw_writel(htobe32(v), addr);
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__io_aw();
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}
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#define iowrite32be(v, addr) iowrite32be(v, addr)
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#if defined(__i386__) || defined(__amd64__)
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static inline void
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_outb(u_char data, u_int port)
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{
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__asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
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}
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#endif
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#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) || defined(__aarch64__)
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void *_ioremap_attr(vm_paddr_t phys_addr, unsigned long size, int attr);
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#else
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#define _ioremap_attr(...) NULL
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#endif
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#ifdef VM_MEMATTR_DEVICE
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#define ioremap_nocache(addr, size) \
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_ioremap_attr((addr), (size), VM_MEMATTR_DEVICE)
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#define ioremap_wt(addr, size) \
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_ioremap_attr((addr), (size), VM_MEMATTR_DEVICE)
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#define ioremap(addr, size) \
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_ioremap_attr((addr), (size), VM_MEMATTR_DEVICE)
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#else
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#define ioremap_nocache(addr, size) \
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_ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE)
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#define ioremap_wt(addr, size) \
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_ioremap_attr((addr), (size), VM_MEMATTR_WRITE_THROUGH)
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#define ioremap(addr, size) \
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_ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE)
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#endif
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#define ioremap_wc(addr, size) \
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_ioremap_attr((addr), (size), VM_MEMATTR_WRITE_COMBINING)
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#define ioremap_wb(addr, size) \
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_ioremap_attr((addr), (size), VM_MEMATTR_WRITE_BACK)
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void iounmap(void *addr);
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#define memset_io(a, b, c) memset((a), (b), (c))
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#define memcpy_fromio(a, b, c) memcpy((a), (b), (c))
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#define memcpy_toio(a, b, c) memcpy((a), (b), (c))
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static inline void
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__iowrite32_copy(void *to, void *from, size_t count)
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{
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uint32_t *src;
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uint32_t *dst;
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int i;
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for (i = 0, src = from, dst = to; i < count; i++, src++, dst++)
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__raw_writel(*src, dst);
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}
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static inline void
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__iowrite64_copy(void *to, void *from, size_t count)
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{
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#ifdef __LP64__
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uint64_t *src;
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uint64_t *dst;
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int i;
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for (i = 0, src = from, dst = to; i < count; i++, src++, dst++)
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__raw_writeq(*src, dst);
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#else
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__iowrite32_copy(to, from, count * 2);
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#endif
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}
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enum {
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MEMREMAP_WB = 1 << 0,
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MEMREMAP_WT = 1 << 1,
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MEMREMAP_WC = 1 << 2,
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};
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static inline void *
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memremap(resource_size_t offset, size_t size, unsigned long flags)
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{
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void *addr = NULL;
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if ((flags & MEMREMAP_WB) &&
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(addr = ioremap_wb(offset, size)) != NULL)
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goto done;
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if ((flags & MEMREMAP_WT) &&
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(addr = ioremap_wt(offset, size)) != NULL)
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goto done;
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if ((flags & MEMREMAP_WC) &&
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(addr = ioremap_wc(offset, size)) != NULL)
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goto done;
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done:
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return (addr);
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}
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static inline void
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memunmap(void *addr)
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{
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/* XXX May need to check if this is RAM */
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iounmap(addr);
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}
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#endif /* _LINUX_IO_H_ */
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