4d91ecaf4c
Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
201 lines
4.9 KiB
C
201 lines
4.9 KiB
C
/*-
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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* NETLOGIC_BSD */
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#ifndef __NLM_MIPS_EXTNS_H__
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#define __NLM_MIPS_EXTNS_H__
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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static __inline__ int32_t nlm_swapw(int32_t *loc, int32_t val)
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{
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int32_t oldval = 0;
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__asm__ __volatile__ (
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".set push\n"
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".set noreorder\n"
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"move $9, %2\n"
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"move $8, %3\n"
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".word 0x71280014\n" /* "swapw $8, $9\n" */
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"move %1, $8\n"
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".set pop\n"
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: "+m" (*loc), "=r" (oldval)
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: "r" (loc), "r" (val)
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: "$8", "$9" );
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return oldval;
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}
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static __inline__ uint32_t nlm_swapwu(int32_t *loc, uint32_t val)
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{
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uint32_t oldval;
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__asm__ __volatile__ (
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".set push\n"
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".set noreorder\n"
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"move $9, %2\n"
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"move $8, %3\n"
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".word 0x71280015\n" /* "swapwu $8, $9\n" */
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"move %1, $8\n"
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".set pop\n"
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: "+m" (*loc), "=r" (oldval)
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: "r" (loc), "r" (val)
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: "$8", "$9" );
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return oldval;
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}
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#if (__mips == 64)
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static __inline__ uint64_t nlm_swapd(int32_t *loc, uint64_t val)
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{
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uint64_t oldval;
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__asm__ __volatile__ (
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".set push\n"
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".set noreorder\n"
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"move $9, %2\n"
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"move $8, %3\n"
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".word 0x71280014\n" /* "swapw $8, $9\n" */
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"move %1, $8\n"
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".set pop\n"
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: "+m" (*loc), "=r" (oldval)
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: "r" (loc), "r" (val)
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: "$8", "$9" );
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return oldval;
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}
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#endif
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#if defined(__mips_n64) || defined(__mips_n32)
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static __inline uint64_t
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nlm_mfcr(uint32_t reg)
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{
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uint64_t res;
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__asm__ __volatile__(
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".set push\n\t"
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".set noreorder\n\t"
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"move $9, %1\n\t"
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".word 0x71280018\n\t" /* mfcr $8, $9 */
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"move %0, $8\n\t"
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".set pop\n"
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: "=r" (res) : "r"(reg)
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: "$8", "$9"
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);
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return (res);
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}
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static __inline void
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nlm_mtcr(uint32_t reg, uint64_t value)
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{
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__asm__ __volatile__(
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".set push\n\t"
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".set noreorder\n\t"
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"move $8, %0\n"
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"move $9, %1\n"
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".word 0x71280019\n" /* mtcr $8, $9 */
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".set pop\n"
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:
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: "r" (value), "r" (reg)
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: "$8", "$9"
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);
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}
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#else /* !(defined(__mips_n64) || defined(__mips_n32)) */
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static __inline__ uint64_t
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nlm_mfcr(uint32_t reg)
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{
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uint64_t hi;
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uint64_t lo;
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__asm__ __volatile__ (
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".set push\n"
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".set mips64\n"
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"move $8, %2\n"
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".word 0x71090018\n"
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"nop \n"
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"dsra32 %0, $9, 0\n"
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"sll %1, $9, 0\n"
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".set pop\n"
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: "=r"(hi), "=r"(lo)
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: "r"(reg) : "$8", "$9");
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return (((uint64_t)hi) << 32) | lo;
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}
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static __inline__ void
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nlm_mtcr(uint32_t reg, uint64_t val)
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{
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uint32_t hi, lo;
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hi = val >> 32;
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lo = val & 0xffffffff;
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__asm__ __volatile__ (
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".set push\n"
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".set mips64\n"
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"move $9, %0\n"
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"dsll32 $9, %1, 0\n"
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"dsll32 $8, %0, 0\n"
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"dsrl32 $9, $9, 0\n"
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"or $9, $9, $8\n"
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"move $8, %2\n"
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".word 0x71090019\n"
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"nop \n"
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".set pop\n"
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::"r"(hi), "r"(lo), "r"(reg)
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: "$8", "$9");
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}
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#endif /* (defined(__mips_n64) || defined(__mips_n32)) */
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/* dcrc2 */
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/* XLP additional instructions */
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/*
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* Atomic increment a unsigned int
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*/
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static __inline unsigned int
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nlm_ldaddwu(unsigned int value, unsigned int *addr)
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{
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__asm__ __volatile__(
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".set push\n"
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".set noreorder\n"
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"move $8, %2\n"
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"move $9, %3\n"
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".word 0x71280011\n" /* ldaddwu $8, $9 */
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"move %0, $8\n"
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".set pop\n"
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: "=&r"(value), "+m"(*addr)
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: "0"(value), "r" ((unsigned long)addr)
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: "$8", "$9");
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return (value);
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}
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#endif
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#endif
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