06152bf0e1
scic_sds_controller_registers.h s/contoller/controller/ PR: 207336 Submitted by: Tony Narlock <tony @ git-pull.com>
599 lines
15 KiB
C
599 lines
15 KiB
C
/*-
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _SCIC_SDS_CONTROLLER_REGISTERS_H_
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#define _SCIC_SDS_CONTROLLER_REGISTERS_H_
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/**
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* @file
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*
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* @brief This file contains macros used to perform the register reads/writes
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* to the SCU hardware.
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif // __cplusplus
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#include <dev/isci/scil/scu_registers.h>
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#include <dev/isci/scil/scic_sds_controller.h>
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/**
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* @name SMU_REGISTER_ACCESS_MACROS
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*/
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/*@{*/
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#define scic_sds_controller_smu_register_read(controller, reg) \
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smu_register_read( \
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(controller), \
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(controller)->smu_registers->reg \
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)
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#define scic_sds_controller_smu_register_write(controller, reg, value) \
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smu_register_write( \
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(controller), \
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(controller)->smu_registers->reg, \
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(value) \
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)
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/*@}*/
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/**
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* @name AFE_REGISTER_ACCESS_MACROS
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*/
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/*@{*/
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#define scu_afe_register_write(controller, reg, value) \
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scu_register_write( \
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(controller), \
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(controller)->scu_registers->afe.reg, \
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(value) \
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)
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#define scu_afe_register_read(controller, reg) \
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scu_register_read( \
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(controller), \
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(controller)->scu_registers->afe.reg \
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)
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/*@}*/
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/**
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* @name SGPIO_PEG0_REGISTER_ACCESS_MACROS
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*/
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/*@{*/
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#define scu_sgpio_peg0_register_read(controller, reg) \
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scu_register_read( \
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(controller), \
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(controller)->scu_registers->peg0.sgpio.reg \
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)
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#define scu_sgpio_peg0_register_write(controller, reg, value) \
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scu_register_write( \
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(controller), \
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(controller)->scu_registers->peg0.sgpio.reg, \
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(value) \
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)
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/*@}*/
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/**
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* @name VIIT_REGISTER_ACCESS_MACROS
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*/
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/*@{*/
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#define scu_controller_viit_register_write(controller, index, reg, value) \
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scu_register_write( \
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(controller), \
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(controller)->scu_registers->peg0.viit[index].reg, \
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value \
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)
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/*@}*/
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/**
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* @name SCRATCH_RAM_REGISTER_ACCESS_MACROS
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*/
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/*@{*/
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// Scratch RAM access may be needed before the scu_registers pointer
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// has been initialized. So instead, explicitly cast BAR1 to a
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// SCU_REGISTERS_T data structure.
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// Scratch RAM is stored in the Zoning Permission Table for OROM use.
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#define scu_controller_scratch_ram_register_write(controller, index, value) \
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scu_register_write( \
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(controller), \
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((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index], \
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value \
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)
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#define scu_controller_scratch_ram_register_read(controller, index) \
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scu_register_read( \
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(controller), \
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((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index] \
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)
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#define scu_controller_scratch_ram_register_write_ext(controller, index, value) \
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scu_register_write( \
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(controller), \
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((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index], \
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value \
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)
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#define scu_controller_scratch_ram_register_read_ext(controller, index) \
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scu_register_read( \
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(controller), \
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((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index] \
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)
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/*@}*/
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//*****************************************************************************
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//* SMU REGISTERS
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//*****************************************************************************
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/**
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* @name SMU_REGISTERS
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*/
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/*@{*/
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#define SMU_PCP_WRITE(controller, value) \
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scic_sds_controller_smu_register_write( \
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controller, post_context_port, value \
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)
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#define SMU_TCR_READ(controller, value) \
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scic_sds_controller_smu_register_read( \
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controller, task_context_range \
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)
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#define SMU_TCR_WRITE(controller, value) \
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scic_sds_controller_smu_register_write( \
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controller, task_context_range, value \
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)
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#define SMU_HTTBAR_WRITE(controller, address) \
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{ \
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scic_sds_controller_smu_register_write( \
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controller, \
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host_task_table_lower, \
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sci_cb_physical_address_lower(address) \
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);\
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scic_sds_controller_smu_register_write( \
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controller, \
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host_task_table_upper, \
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sci_cb_physical_address_upper(address) \
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); \
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}
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#define SMU_CQBAR_WRITE(controller, address) \
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{ \
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scic_sds_controller_smu_register_write( \
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controller, \
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completion_queue_lower, \
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sci_cb_physical_address_lower(address) \
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); \
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scic_sds_controller_smu_register_write( \
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controller, \
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completion_queue_upper, \
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sci_cb_physical_address_upper(address) \
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); \
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}
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#define SMU_CQGR_WRITE(controller, value) \
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scic_sds_controller_smu_register_write( \
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controller, completion_queue_get, value \
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)
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#define SMU_CQGR_READ(controller, value) \
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scic_sds_controller_smu_register_read( \
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controller, completion_queue_get \
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)
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#define SMU_CQPR_WRITE(controller, value) \
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scic_sds_controller_smu_register_write( \
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controller, completion_queue_put, value \
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)
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#define SMU_RNCBAR_WRITE(controller, address) \
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{ \
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scic_sds_controller_smu_register_write( \
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controller, \
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remote_node_context_lower, \
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sci_cb_physical_address_lower(address) \
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); \
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scic_sds_controller_smu_register_write( \
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controller, \
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remote_node_context_upper, \
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sci_cb_physical_address_upper(address) \
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); \
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}
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#define SMU_AMR_READ(controller) \
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scic_sds_controller_smu_register_read( \
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controller, address_modifier \
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)
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#define SMU_IMR_READ(controller) \
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scic_sds_controller_smu_register_read( \
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controller, interrupt_mask \
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)
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#define SMU_IMR_WRITE(controller, mask) \
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scic_sds_controller_smu_register_write( \
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controller, interrupt_mask, mask \
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)
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#define SMU_ISR_READ(controller) \
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scic_sds_controller_smu_register_read( \
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controller, interrupt_status \
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)
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#define SMU_ISR_WRITE(controller, status) \
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scic_sds_controller_smu_register_write( \
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controller, interrupt_status, status \
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)
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#define SMU_ICC_READ(controller) \
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scic_sds_controller_smu_register_read( \
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controller, interrupt_coalesce_control \
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)
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#define SMU_ICC_WRITE(controller, value) \
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scic_sds_controller_smu_register_write( \
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controller, interrupt_coalesce_control, value \
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)
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#define SMU_CQC_WRITE(controller, value) \
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scic_sds_controller_smu_register_write( \
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controller, completion_queue_control, value \
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)
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#define SMU_SMUSRCR_WRITE(controller, value) \
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scic_sds_controller_smu_register_write( \
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controller, soft_reset_control, value \
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)
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#define SMU_TCA_WRITE(controller, index, value) \
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scic_sds_controller_smu_register_write( \
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controller, task_context_assignment[index], value \
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)
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#define SMU_TCA_READ(controller, index) \
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scic_sds_controller_smu_register_read( \
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controller, task_context_assignment[index] \
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)
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#define SMU_DCC_READ(controller) \
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scic_sds_controller_smu_register_read( \
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controller, device_context_capacity \
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)
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#define SMU_DFC_READ(controller) \
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scic_sds_controller_smu_register_read( \
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controller, device_function_capacity \
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)
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#define SMU_SMUCSR_READ(controller) \
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scic_sds_controller_smu_register_read( \
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controller, control_status \
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)
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#define SMU_CGUCR_READ(controller) \
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scic_sds_controller_smu_register_read( \
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controller, clock_gating_control \
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)
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#define SMU_CGUCR_WRITE(controller, value) \
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scic_sds_controller_smu_register_write( \
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controller, clock_gating_control, value \
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)
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#define SMU_CQPR_READ(controller) \
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scic_sds_controller_smu_register_read( \
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controller, completion_queue_put \
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)
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/*@}*/
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/**
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* @name SCU_REGISTER_ACCESS_MACROS
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*/
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/*@{*/
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#define scic_sds_controller_scu_register_read(controller, reg) \
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scu_register_read( \
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(controller), \
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(controller)->scu_registers->reg \
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)
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#define scic_sds_controller_scu_register_write(controller, reg, value) \
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scu_register_write( \
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(controller), \
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(controller)->scu_registers->reg, \
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(value) \
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)
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/*@}*/
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//****************************************************************************
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//* SCU SDMA REGISTERS
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//****************************************************************************
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/**
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* @name SCU_SDMA_REGISTER_ACCESS_MACROS
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*/
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/*@{*/
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#define scu_sdma_register_read(controller, reg) \
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scu_register_read( \
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(controller), \
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(controller)->scu_registers->sdma.reg \
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)
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#define scu_sdma_register_write(controller, reg, value) \
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scu_register_write( \
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(controller), \
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(controller)->scu_registers->sdma.reg, \
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(value) \
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)
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/*@}*/
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/**
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* @name SCU_SDMA_REGISTERS
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*/
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/*@{*/
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#define SCU_PUFATHAR_WRITE(controller, address) \
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{ \
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scu_sdma_register_write( \
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controller, \
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uf_address_table_lower, \
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sci_cb_physical_address_lower(address) \
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); \
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scu_sdma_register_write( \
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controller, \
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uf_address_table_upper, \
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sci_cb_physical_address_upper(address) \
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); \
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}
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#define SCU_UFHBAR_WRITE(controller, address) \
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{ \
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scu_sdma_register_write( \
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controller, \
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uf_header_base_address_lower, \
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sci_cb_physical_address_lower(address) \
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); \
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scu_sdma_register_write( \
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controller, \
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uf_header_base_address_upper, \
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sci_cb_physical_address_upper(address) \
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); \
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}
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#define SCU_UFQC_READ(controller) \
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scu_sdma_register_read( \
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controller, \
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unsolicited_frame_queue_control \
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)
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#define SCU_UFQC_WRITE(controller, value) \
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scu_sdma_register_write( \
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controller, \
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unsolicited_frame_queue_control, \
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value \
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)
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#define SCU_UFQPP_READ(controller) \
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scu_sdma_register_read( \
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controller, \
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unsolicited_frame_put_pointer \
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)
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#define SCU_UFQPP_WRITE(controller, value) \
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scu_sdma_register_write( \
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controller, \
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unsolicited_frame_put_pointer, \
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value \
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)
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#define SCU_UFQGP_WRITE(controller, value) \
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scu_sdma_register_write( \
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controller, \
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unsolicited_frame_get_pointer, \
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value \
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)
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#define SCU_PDMACR_READ(controller) \
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scu_sdma_register_read( \
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controller, \
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pdma_configuration \
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)
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#define SCU_PDMACR_WRITE(controller, value) \
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scu_sdma_register_write( \
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controller, \
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pdma_configuration, \
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value \
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)
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#define SCU_CDMACR_READ(controller) \
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scu_sdma_register_read( \
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controller, \
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cdma_configuration \
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)
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#define SCU_CDMACR_WRITE(controller, value) \
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scu_sdma_register_write( \
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controller, \
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cdma_configuration, \
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value \
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)
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/*@}*/
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//*****************************************************************************
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//* SCU CRAM AND FBRAM Registers
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//*****************************************************************************
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/**
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* @name SCU_CRAM_REGISTER_ACCESS_MACROS
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*/
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/*@{*/
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#define scu_cram_register_read(controller, reg) \
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scu_register_read( \
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(controller), \
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(controller)->scu_registers->cram.reg \
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)
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#define scu_cram_register_write(controller, reg, value) \
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scu_register_write( \
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(controller), \
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(controller)->scu_registers->cram.reg, \
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(value) \
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)
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/*@}*/
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/**
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* @name SCU_FBRAM_REGISTER_ACCESS_MACROS
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*/
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/*@{*/
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#define scu_fbram_register_read(controller, reg) \
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scu_register_read( \
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(controller), \
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(controller)->scu_registers->fbram.reg \
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)
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#define scu_fbram_register_write(controller, reg, value) \
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scu_register_write( \
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(controller), \
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(controller)->scu_registers->fbram.reg, \
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(value) \
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)
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/*@}*/
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|
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/**
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* @name SCU_CRAM_REGISTERS
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|
*/
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/*@{*/
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// SRAM ECC CONTROL REGISTER BITS
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#define SIGNLE_BIT_ERROR_CORRECTION_ENABLE 0x00000001
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#define MULTI_BIT_ERROR_REPORTING_ENABLE 0x00000002
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#define SINGLE_BIT_ERROR_REPORTING_ENABLE 0x00000004
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|
|
//SRAM ECC control register (SECR0)
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#define SCU_SECR0_WRITE(controller, value) \
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scu_cram_register_write( \
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controller, \
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sram_ecc_control_0, \
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value \
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)
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|
/*@}*/
|
|
|
|
/**
|
|
* @name SCU_FBRAM_REGISTERS
|
|
*/
|
|
/*@{*/
|
|
|
|
//SRAM ECC control register (SECR1)
|
|
#define SCU_SECR1_WRITE(controller, value) \
|
|
scu_fbram_register_write( \
|
|
controller, \
|
|
sram_ecc_control_1, \
|
|
value \
|
|
)
|
|
/*@}*/
|
|
|
|
|
|
//*****************************************************************************
|
|
//* SCU Port Task Scheduler Group Registers
|
|
//*****************************************************************************
|
|
|
|
/**
|
|
* @name SCU_PTSG_REGISTER_ACCESS_MACROS
|
|
*/
|
|
/*@{*/
|
|
#define scu_ptsg_register_read(controller, reg) \
|
|
scu_register_read( \
|
|
(controller), \
|
|
(controller)->scu_registers->peg0.ptsg.reg \
|
|
)
|
|
|
|
#define scu_ptsg_register_write(controller, reg, value) \
|
|
scu_register_write( \
|
|
(controller), \
|
|
(controller)->scu_registers->peg0.ptsg.reg, \
|
|
(value) \
|
|
)
|
|
/*@}*/
|
|
|
|
/**
|
|
* @name SCU_PTSG_REGISTERS
|
|
*/
|
|
/*@{*/
|
|
#define SCU_PTSGCR_READ(controller) \
|
|
scu_ptsg_register_read( \
|
|
(controller), \
|
|
control \
|
|
)
|
|
|
|
#define SCU_PTSGCR_WRITE(controller, value) \
|
|
scu_ptsg_register_write( \
|
|
(controller), \
|
|
control, \
|
|
value \
|
|
)
|
|
|
|
#define SCU_PTSGRTC_READ(controller) \
|
|
scu_ptsg_register_read( \
|
|
controller, \
|
|
real_time_clock \
|
|
)
|
|
/*@}*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif // __cplusplus
|
|
|
|
#endif // _SCIC_SDS_CONTROLLER_REGISTERS_H_
|