254 lines
7.4 KiB
ArmAsm
254 lines
7.4 KiB
ArmAsm
/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $FreeBSD$
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*/
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#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
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#define IRQ_LBIT(irq_num) (1 << (irq_num))
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#define IRQ_BYTE(irq_num) ((irq_num) >> 3)
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#ifdef AUTO_EOI_1
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#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
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#define OUTB_ICU1
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#else
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#define ENABLE_ICU1 \
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movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
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OUTB_ICU1 /* ... to clear in service bit */
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#define OUTB_ICU1 \
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outb %al,$IO_ICU1
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#endif
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#ifdef AUTO_EOI_2
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/*
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* The data sheet says no auto-EOI on slave, but it sometimes works.
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*/
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#define ENABLE_ICU1_AND_2 ENABLE_ICU1
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#else
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#define ENABLE_ICU1_AND_2 \
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movb $ICU_EOI,%al ; /* as above */ \
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outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
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OUTB_ICU1 /* ... then first icu (if !AUTO_EOI_1) */
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#endif
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#define PUSH_FRAME \
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pushl $0 ; /* dummy error code */ \
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pushl $0 ; /* dummy trap type */ \
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pushal ; /* 8 ints */ \
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pushl %ds ; /* save data and extra segments ... */ \
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pushl %es ; \
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pushl %fs
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#define PUSH_DUMMY \
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pushfl ; /* eflags */ \
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pushl %cs ; /* cs */ \
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pushl 12(%esp) ; /* original caller eip */ \
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pushl $0 ; /* dummy error code */ \
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pushl $0 ; /* dummy trap type */ \
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subl $11*4,%esp
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#define POP_FRAME \
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popl %fs ; \
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popl %es ; \
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popl %ds ; \
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popal ; \
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addl $4+4,%esp
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#define POP_DUMMY \
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addl $16*4,%esp
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#define MASK_IRQ(icu, irq_num) \
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movb imen + IRQ_BYTE(irq_num),%al ; \
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orb $IRQ_BIT(irq_num),%al ; \
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movb %al,imen + IRQ_BYTE(irq_num) ; \
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outb %al,$icu+ICU_IMR_OFFSET
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#define UNMASK_IRQ(icu, irq_num) \
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movb imen + IRQ_BYTE(irq_num),%al ; \
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andb $~IRQ_BIT(irq_num),%al ; \
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movb %al,imen + IRQ_BYTE(irq_num) ; \
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outb %al,$icu+ICU_IMR_OFFSET
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/*
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* Macros for interrupt interrupt entry, call to handler, and exit.
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*/
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#define FAST_INTR(irq_num, vec_name, icu, enable_icus) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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PUSH_FRAME ; \
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mov $KDSEL,%ax ; \
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mov %ax,%ds ; \
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mov %ax,%es ; \
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mov $KPSEL,%ax ; \
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mov %ax,%fs ; \
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FAKE_MCOUNT((12+ACTUALLY_PUSHED)*4(%esp)) ; \
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movl PCPU(CURTHREAD),%ebx ; \
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cmpl $0,TD_CRITNEST(%ebx) ; \
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je 1f ; \
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; \
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movl $1,PCPU(INT_PENDING) ; \
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orl $IRQ_LBIT(irq_num),PCPU(FPENDING) ; \
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MASK_IRQ(icu, irq_num) ; \
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enable_icus ; \
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jmp 10f ; \
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1: ; \
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incl TD_CRITNEST(%ebx) ; \
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incl TD_INTR_NESTING_LEVEL(%ebx) ; \
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pushl intr_unit + (irq_num) * 4 ; \
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call *intr_handler + (irq_num) * 4 ; \
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addl $4,%esp ; \
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enable_icus ; \
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incl cnt+V_INTR ; /* book-keeping can wait */ \
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movl intr_countp + (irq_num) * 4,%eax ; \
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incl (%eax) ; \
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decl TD_CRITNEST(%ebx) ; \
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cmpl $0,PCPU(INT_PENDING) ; \
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je 2f ; \
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; \
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call i386_unpend ; \
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2: ; \
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decl TD_INTR_NESTING_LEVEL(%ebx) ; \
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10: ; \
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MEXITCOUNT ; \
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jmp doreti
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/*
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* Restart a fast interrupt that was held up by a critical section.
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* This routine is called from unpend(). unpend() ensures we are
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* in a critical section and deals with the interrupt nesting level
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* for us. If we previously masked the irq, we have to unmask it.
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*
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* We have a choice. We can regenerate the irq using the 'int'
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* instruction or we can create a dummy frame and call the interrupt
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* handler directly. I've chosen to use the dummy-frame method.
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*/
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#define FAST_UNPEND(irq_num, vec_name, icu) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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; \
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pushl %ebp ; \
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movl %esp, %ebp ; \
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PUSH_DUMMY ; \
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pushl intr_unit + (irq_num) * 4 ; \
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call *intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
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addl $4, %esp ; \
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incl cnt+V_INTR ; /* book-keeping can wait */ \
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movl intr_countp + (irq_num) * 4,%eax ; \
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incl (%eax) ; \
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UNMASK_IRQ(icu, irq_num) ; \
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POP_DUMMY ; \
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popl %ebp ; \
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ret
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/*
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* Slow, threaded interrupts.
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*
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* XXX Most of the parameters here are obsolete. Fix this when we're
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* done.
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* XXX we really shouldn't return via doreti if we just schedule the
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* interrupt handler and don't run anything. We could just do an
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* iret. FIXME.
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*/
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#define INTR(irq_num, vec_name, icu, enable_icus, maybe_extra_ipending) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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PUSH_FRAME ; \
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mov $KDSEL,%ax ; /* load kernel ds, es and fs */ \
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mov %ax,%ds ; \
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mov %ax,%es ; \
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mov $KPSEL,%ax ; \
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mov %ax,%fs ; \
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; \
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maybe_extra_ipending ; \
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MASK_IRQ(icu, irq_num) ; \
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enable_icus ; \
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; \
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movl PCPU(CURTHREAD),%ebx ; \
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cmpl $0,TD_CRITNEST(%ebx) ; \
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je 1f ; \
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movl $1,PCPU(INT_PENDING); \
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orl $IRQ_LBIT(irq_num),PCPU(IPENDING) ; \
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jmp 10f ; \
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1: ; \
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incl TD_INTR_NESTING_LEVEL(%ebx) ; \
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; \
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FAKE_MCOUNT(13*4(%esp)) ; /* XXX late to avoid double count */ \
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cmpl $0,PCPU(INT_PENDING) ; \
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je 9f ; \
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call i386_unpend ; \
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9: ; \
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pushl $irq_num; /* pass the IRQ */ \
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call sched_ithd ; \
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addl $4, %esp ; /* discard the parameter */ \
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; \
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decl TD_INTR_NESTING_LEVEL(%ebx) ; \
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10: ; \
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MEXITCOUNT ; \
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jmp doreti
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MCOUNT_LABEL(bintr)
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FAST_INTR(0,fastintr0, IO_ICU1, ENABLE_ICU1)
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FAST_INTR(1,fastintr1, IO_ICU1, ENABLE_ICU1)
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FAST_INTR(2,fastintr2, IO_ICU1, ENABLE_ICU1)
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FAST_INTR(3,fastintr3, IO_ICU1, ENABLE_ICU1)
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FAST_INTR(4,fastintr4, IO_ICU1, ENABLE_ICU1)
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FAST_INTR(5,fastintr5, IO_ICU1, ENABLE_ICU1)
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FAST_INTR(6,fastintr6, IO_ICU1, ENABLE_ICU1)
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FAST_INTR(7,fastintr7, IO_ICU1, ENABLE_ICU1)
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FAST_INTR(8,fastintr8, IO_ICU2, ENABLE_ICU1_AND_2)
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FAST_INTR(9,fastintr9, IO_ICU2, ENABLE_ICU1_AND_2)
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FAST_INTR(10,fastintr10, IO_ICU2, ENABLE_ICU1_AND_2)
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FAST_INTR(11,fastintr11, IO_ICU2, ENABLE_ICU1_AND_2)
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FAST_INTR(12,fastintr12, IO_ICU2, ENABLE_ICU1_AND_2)
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FAST_INTR(13,fastintr13, IO_ICU2, ENABLE_ICU1_AND_2)
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FAST_INTR(14,fastintr14, IO_ICU2, ENABLE_ICU1_AND_2)
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FAST_INTR(15,fastintr15, IO_ICU2, ENABLE_ICU1_AND_2)
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#define CLKINTR_PENDING movl $1,CNAME(clkintr_pending)
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/* Threaded interrupts */
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INTR(0,intr0, IO_ICU1, ENABLE_ICU1, CLKINTR_PENDING)
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INTR(1,intr1, IO_ICU1, ENABLE_ICU1,)
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INTR(2,intr2, IO_ICU1, ENABLE_ICU1,)
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INTR(3,intr3, IO_ICU1, ENABLE_ICU1,)
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INTR(4,intr4, IO_ICU1, ENABLE_ICU1,)
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INTR(5,intr5, IO_ICU1, ENABLE_ICU1,)
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INTR(6,intr6, IO_ICU1, ENABLE_ICU1,)
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INTR(7,intr7, IO_ICU1, ENABLE_ICU1,)
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INTR(8,intr8, IO_ICU2, ENABLE_ICU1_AND_2,)
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INTR(9,intr9, IO_ICU2, ENABLE_ICU1_AND_2,)
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INTR(10,intr10, IO_ICU2, ENABLE_ICU1_AND_2,)
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INTR(11,intr11, IO_ICU2, ENABLE_ICU1_AND_2,)
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INTR(12,intr12, IO_ICU2, ENABLE_ICU1_AND_2,)
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INTR(13,intr13, IO_ICU2, ENABLE_ICU1_AND_2,)
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INTR(14,intr14, IO_ICU2, ENABLE_ICU1_AND_2,)
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INTR(15,intr15, IO_ICU2, ENABLE_ICU1_AND_2,)
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FAST_UNPEND(0,fastunpend0, IO_ICU1)
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FAST_UNPEND(1,fastunpend1, IO_ICU1)
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FAST_UNPEND(2,fastunpend2, IO_ICU1)
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FAST_UNPEND(3,fastunpend3, IO_ICU1)
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FAST_UNPEND(4,fastunpend4, IO_ICU1)
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FAST_UNPEND(5,fastunpend5, IO_ICU1)
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FAST_UNPEND(6,fastunpend6, IO_ICU1)
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FAST_UNPEND(7,fastunpend7, IO_ICU1)
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FAST_UNPEND(8,fastunpend8, IO_ICU2)
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FAST_UNPEND(9,fastunpend9, IO_ICU2)
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FAST_UNPEND(10,fastunpend10, IO_ICU2)
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FAST_UNPEND(11,fastunpend11, IO_ICU2)
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FAST_UNPEND(12,fastunpend12, IO_ICU2)
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FAST_UNPEND(13,fastunpend13, IO_ICU2)
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FAST_UNPEND(14,fastunpend14, IO_ICU2)
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FAST_UNPEND(15,fastunpend15, IO_ICU2)
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MCOUNT_LABEL(eintr)
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