859 lines
25 KiB
C
859 lines
25 KiB
C
/*-
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* Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#ifndef ECORE_INIT_H
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#define ECORE_INIT_H
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/* Init operation types and structures */
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enum {
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OP_RD = 0x1, /* read a single register */
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OP_WR, /* write a single register */
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OP_SW, /* copy a string to the device */
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OP_ZR, /* clear memory */
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OP_ZP, /* unzip then copy with DMAE */
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OP_WR_64, /* write 64 bit pattern */
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OP_WB, /* copy a string using DMAE */
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#ifndef FW_ZIP_SUPPORT
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OP_FW, /* copy an array from fw data (only used with unzipped FW) */
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#endif
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OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */
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OP_IF_MODE_OR, /* Skip the following ops if all init modes don't match */
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OP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */
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OP_IF_PHASE,
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OP_RT,
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OP_DELAY,
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OP_VERIFY,
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OP_MAX
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};
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enum {
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STAGE_START,
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STAGE_END,
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};
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/* Returns the index of start or end of a specific block stage in ops array*/
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#define BLOCK_OPS_IDX(block, stage, end) \
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(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
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/* structs for the various opcodes */
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struct raw_op {
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uint32_t op:8;
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uint32_t offset:24;
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uint32_t raw_data;
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};
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struct op_read {
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uint32_t op:8;
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uint32_t offset:24;
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uint32_t val;
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};
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struct op_write {
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uint32_t op:8;
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uint32_t offset:24;
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uint32_t val;
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};
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struct op_arr_write {
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uint32_t op:8;
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uint32_t offset:24;
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#ifdef __BIG_ENDIAN
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uint16_t data_len;
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uint16_t data_off;
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#else /* __LITTLE_ENDIAN */
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uint16_t data_off;
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uint16_t data_len;
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#endif
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};
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struct op_zero {
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uint32_t op:8;
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uint32_t offset:24;
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uint32_t len;
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};
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struct op_if_mode {
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uint32_t op:8;
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uint32_t cmd_offset:24;
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uint32_t mode_bit_map;
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};
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struct op_if_phase {
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uint32_t op:8;
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uint32_t cmd_offset:24;
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uint32_t phase_bit_map;
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};
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struct op_delay {
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uint32_t op:8;
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uint32_t reserved:24;
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uint32_t delay;
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};
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union init_op {
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struct op_read read;
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struct op_write write;
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struct op_arr_write arr_wr;
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struct op_zero zero;
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struct raw_op raw;
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struct op_if_mode if_mode;
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struct op_if_phase if_phase;
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struct op_delay delay;
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};
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/* Init Phases */
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enum {
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PHASE_COMMON,
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PHASE_PORT0,
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PHASE_PORT1,
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PHASE_PF0,
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PHASE_PF1,
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PHASE_PF2,
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PHASE_PF3,
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PHASE_PF4,
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PHASE_PF5,
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PHASE_PF6,
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PHASE_PF7,
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NUM_OF_INIT_PHASES
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};
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/* Init Modes */
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enum {
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MODE_ASIC = 0x00000001,
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MODE_FPGA = 0x00000002,
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MODE_EMUL = 0x00000004,
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MODE_E2 = 0x00000008,
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MODE_E3 = 0x00000010,
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MODE_PORT2 = 0x00000020,
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MODE_PORT4 = 0x00000040,
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MODE_SF = 0x00000080,
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MODE_MF = 0x00000100,
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MODE_MF_SD = 0x00000200,
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MODE_MF_SI = 0x00000400,
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MODE_MF_AFEX = 0x00000800,
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MODE_E3_A0 = 0x00001000,
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MODE_E3_B0 = 0x00002000,
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MODE_COS3 = 0x00004000,
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MODE_COS6 = 0x00008000,
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MODE_LITTLE_ENDIAN = 0x00010000,
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MODE_BIG_ENDIAN = 0x00020000,
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};
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/* Init Blocks */
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enum {
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BLOCK_ATC,
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BLOCK_BRB1,
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BLOCK_CCM,
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BLOCK_CDU,
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BLOCK_CFC,
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BLOCK_CSDM,
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BLOCK_CSEM,
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BLOCK_DBG,
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BLOCK_DMAE,
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BLOCK_DORQ,
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BLOCK_HC,
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BLOCK_IGU,
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BLOCK_MISC,
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BLOCK_NIG,
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BLOCK_PBF,
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BLOCK_PGLUE_B,
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BLOCK_PRS,
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BLOCK_PXP2,
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BLOCK_PXP,
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BLOCK_QM,
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BLOCK_SRC,
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BLOCK_TCM,
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BLOCK_TM,
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BLOCK_TSDM,
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BLOCK_TSEM,
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BLOCK_UCM,
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BLOCK_UPB,
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BLOCK_USDM,
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BLOCK_USEM,
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BLOCK_XCM,
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BLOCK_XPB,
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BLOCK_XSDM,
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BLOCK_XSEM,
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BLOCK_MISC_AEU,
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NUM_OF_INIT_BLOCKS
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};
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/* Vnics per mode */
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#define ECORE_PORT2_MODE_NUM_VNICS 4
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/* QM queue numbers */
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#define ECORE_ETH_Q 0
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#define ECORE_TOE_Q 3
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#define ECORE_TOE_ACK_Q 6
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#define ECORE_ISCSI_Q 9
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#define ECORE_ISCSI_ACK_Q 11
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#define ECORE_FCOE_Q 10
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/* Vnics per mode */
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#define ECORE_PORT4_MODE_NUM_VNICS 2
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/* COS offset for port1 in E3 B0 4port mode */
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#define ECORE_E3B0_PORT1_COS_OFFSET 3
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/* QM Register addresses */
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#define ECORE_Q_VOQ_REG_ADDR(pf_q_num)\
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(QM_REG_QVOQIDX_0 + 4 * (pf_q_num))
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#define ECORE_VOQ_Q_REG_ADDR(cos, pf_q_num)\
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(QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))
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#define ECORE_Q_CMDQ_REG_ADDR(pf_q_num)\
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(QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))
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/* extracts the QM queue number for the specified port and vnic */
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#define ECORE_PF_Q_NUM(q_num, port, vnic)\
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((((port) << 1) | (vnic)) * 16 + (q_num))
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/* Maps the specified queue to the specified COS */
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static inline void ecore_map_q_cos(struct bxe_softc *sc, uint32_t q_num, uint32_t new_cos)
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{
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/* find current COS mapping */
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uint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4);
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/* check if queue->COS mapping has changed */
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if (curr_cos != new_cos) {
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uint32_t num_vnics = ECORE_PORT2_MODE_NUM_VNICS;
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uint32_t reg_addr, reg_bit_map, vnic;
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/* update parameters for 4port mode */
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if (INIT_MODE_FLAGS(sc) & MODE_PORT4) {
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num_vnics = ECORE_PORT4_MODE_NUM_VNICS;
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if (PORT_ID(sc)) {
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curr_cos += ECORE_E3B0_PORT1_COS_OFFSET;
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new_cos += ECORE_E3B0_PORT1_COS_OFFSET;
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}
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}
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/* change queue mapping for each VNIC */
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for (vnic = 0; vnic < num_vnics; vnic++) {
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uint32_t pf_q_num =
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ECORE_PF_Q_NUM(q_num, PORT_ID(sc), vnic);
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uint32_t q_bit_map = 1 << (pf_q_num & 0x1f);
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/* overwrite queue->VOQ mapping */
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REG_WR(sc, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
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/* clear queue bit from current COS bit map */
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reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);
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reg_bit_map = REG_RD(sc, reg_addr);
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REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map));
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/* set queue bit in new COS bit map */
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reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num);
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reg_bit_map = REG_RD(sc, reg_addr);
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REG_WR(sc, reg_addr, reg_bit_map | q_bit_map);
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/* set/clear queue bit in command-queue bit map
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(E2/E3A0 only, valid COS values are 0/1) */
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if (!(INIT_MODE_FLAGS(sc) & MODE_E3_B0)) {
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reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num);
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reg_bit_map = REG_RD(sc, reg_addr);
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q_bit_map = 1 << (2 * (pf_q_num & 0xf));
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reg_bit_map = new_cos ?
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(reg_bit_map | q_bit_map) :
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(reg_bit_map & (~q_bit_map));
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REG_WR(sc, reg_addr, reg_bit_map);
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}
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}
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}
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}
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/* Configures the QM according to the specified per-traffic-type COSes */
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static inline void ecore_dcb_config_qm(struct bxe_softc *sc, enum cos_mode mode,
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struct priority_cos *traffic_cos)
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{
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ecore_map_q_cos(sc, ECORE_FCOE_Q,
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traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos);
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ecore_map_q_cos(sc, ECORE_ISCSI_Q,
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traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
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ecore_map_q_cos(sc, ECORE_ISCSI_ACK_Q,
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traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
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if (mode != STATIC_COS) {
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/* required only in OVERRIDE_COS mode */
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ecore_map_q_cos(sc, ECORE_ETH_Q,
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traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
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ecore_map_q_cos(sc, ECORE_TOE_Q,
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traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
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ecore_map_q_cos(sc, ECORE_TOE_ACK_Q,
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traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
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}
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}
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/*
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* congestion managment port init api description
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* the api works as follows:
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* the driver should pass the cmng_init_input struct, the port_init function
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* will prepare the required internal ram structure which will be passed back
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* to the driver (cmng_init) that will write it into the internal ram.
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*
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* IMPORTANT REMARKS:
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* 1. the cmng_init struct does not represent the contiguous internal ram
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* structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET
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* offset in order to write the port sub struct and the
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* PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other
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* words - don't use memcpy!).
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* 2. although the cmng_init struct is filled for the maximal vnic number
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* possible, the driver should only write the valid vnics into the internal
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* ram according to the appropriate port mode.
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*/
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#define BITS_TO_BYTES(x) ((x)/8)
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/* CMNG constants, as derived from system spec calculations */
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/* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */
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#define DEF_MIN_RATE 100
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/* resolution of the rate shaping timer - 400 usec */
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#define RS_PERIODIC_TIMEOUT_USEC 400
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/*
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* number of bytes in single QM arbitration cycle -
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* coefficient for calculating the fairness timer
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*/
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#define QM_ARB_BYTES 160000
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/* resolution of Min algorithm 1:100 */
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#define MIN_RES 100
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/*
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* how many bytes above threshold for
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* the minimal credit of Min algorithm
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*/
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#define MIN_ABOVE_THRESH 32768
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/*
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* Fairness algorithm integration time coefficient -
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* for calculating the actual Tfair
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*/
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#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
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/* Memory of fairness algorithm - 2 cycles */
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#define FAIR_MEM 2
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#define SAFC_TIMEOUT_USEC 52
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#define SDM_TICKS 4
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static inline void ecore_init_max(const struct cmng_init_input *input_data,
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uint32_t r_param, struct cmng_init *ram_data)
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{
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uint32_t vnic;
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struct cmng_vnic *vdata = &ram_data->vnic;
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struct cmng_struct_per_port *pdata = &ram_data->port;
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/*
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* rate shaping per-port variables
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* 100 micro seconds in SDM ticks = 25
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* since each tick is 4 microSeconds
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*/
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pdata->rs_vars.rs_periodic_timeout =
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RS_PERIODIC_TIMEOUT_USEC / SDM_TICKS;
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/* this is the threshold below which no timer arming will occur.
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* 1.25 coefficient is for the threshold to be a little bigger
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* then the real time to compensate for timer in-accuracy
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*/
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pdata->rs_vars.rs_threshold =
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(5 * RS_PERIODIC_TIMEOUT_USEC * r_param)/4;
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/* rate shaping per-vnic variables */
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for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
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/* global vnic counter */
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vdata->vnic_max_rate[vnic].vn_counter.rate =
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input_data->vnic_max_rate[vnic];
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/*
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* maximal Mbps for this vnic
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* the quota in each timer period - number of bytes
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* transmitted in this period
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*/
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vdata->vnic_max_rate[vnic].vn_counter.quota =
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RS_PERIODIC_TIMEOUT_USEC *
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(uint32_t)vdata->vnic_max_rate[vnic].vn_counter.rate / 8;
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}
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}
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static inline void ecore_init_max_per_vn(uint16_t vnic_max_rate,
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struct rate_shaping_vars_per_vn *ram_data)
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{
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/* global vnic counter */
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ram_data->vn_counter.rate = vnic_max_rate;
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/*
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* maximal Mbps for this vnic
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* the quota in each timer period - number of bytes
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* transmitted in this period
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*/
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ram_data->vn_counter.quota =
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RS_PERIODIC_TIMEOUT_USEC * (uint32_t)vnic_max_rate / 8;
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}
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static inline void ecore_init_min(const struct cmng_init_input *input_data,
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uint32_t r_param, struct cmng_init *ram_data)
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{
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uint32_t vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair;
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struct cmng_vnic *vdata = &ram_data->vnic;
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struct cmng_struct_per_port *pdata = &ram_data->port;
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/* this is the resolution of the fairness timer */
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fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
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/*
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* fairness per-port variables
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* for 10G it is 1000usec. for 1G it is 10000usec.
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*/
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tFair = T_FAIR_COEF / input_data->port_rate;
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/* this is the threshold below which we won't arm the timer anymore */
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pdata->fair_vars.fair_threshold = QM_ARB_BYTES;
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/*
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* we multiply by 1e3/8 to get bytes/msec. We don't want the credits
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* to pass a credit of the T_FAIR*FAIR_MEM (algorithm resolution)
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*/
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pdata->fair_vars.upper_bound = r_param * tFair * FAIR_MEM;
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/* since each tick is 4 microSeconds */
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pdata->fair_vars.fairness_timeout =
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fair_periodic_timeout_usec / SDM_TICKS;
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/* calculate sum of weights */
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vnicWeightSum = 0;
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for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++)
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vnicWeightSum += input_data->vnic_min_rate[vnic];
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/* global vnic counter */
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if (vnicWeightSum > 0) {
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/* fairness per-vnic variables */
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for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
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/*
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* this is the credit for each period of the fairness
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* algorithm - number of bytes in T_FAIR (this vnic
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* share of the port rate)
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*/
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vdata->vnic_min_rate[vnic].vn_credit_delta =
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((uint32_t)(input_data->vnic_min_rate[vnic]) * 100 *
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(T_FAIR_COEF / (8 * 100 * vnicWeightSum)));
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if (vdata->vnic_min_rate[vnic].vn_credit_delta <
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pdata->fair_vars.fair_threshold +
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MIN_ABOVE_THRESH) {
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vdata->vnic_min_rate[vnic].vn_credit_delta =
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pdata->fair_vars.fair_threshold +
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MIN_ABOVE_THRESH;
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}
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}
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}
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}
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static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,
|
|
uint32_t r_param, struct cmng_init *ram_data)
|
|
{
|
|
uint32_t vnic, cos;
|
|
uint32_t cosWeightSum = 0;
|
|
struct cmng_vnic *vdata = &ram_data->vnic;
|
|
struct cmng_struct_per_port *pdata = &ram_data->port;
|
|
|
|
for (cos = 0; cos < MAX_COS_NUMBER; cos++)
|
|
cosWeightSum += input_data->cos_min_rate[cos];
|
|
|
|
if (cosWeightSum > 0) {
|
|
|
|
for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
|
|
/*
|
|
* Since cos and vnic shouldn't work together the rate
|
|
* to divide between the coses is the port rate.
|
|
*/
|
|
uint32_t *ccd = vdata->vnic_min_rate[vnic].cos_credit_delta;
|
|
for (cos = 0; cos < MAX_COS_NUMBER; cos++) {
|
|
/*
|
|
* this is the credit for each period of
|
|
* the fairness algorithm - number of bytes
|
|
* in T_FAIR (this cos share of the vnic rate)
|
|
*/
|
|
ccd[cos] =
|
|
((uint32_t)input_data->cos_min_rate[cos] * 100 *
|
|
(T_FAIR_COEF / (8 * 100 * cosWeightSum)));
|
|
if (ccd[cos] < pdata->fair_vars.fair_threshold
|
|
+ MIN_ABOVE_THRESH) {
|
|
ccd[cos] =
|
|
pdata->fair_vars.fair_threshold +
|
|
MIN_ABOVE_THRESH;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static inline void ecore_init_safc(const struct cmng_init_input *input_data,
|
|
struct cmng_init *ram_data)
|
|
{
|
|
/* in microSeconds */
|
|
ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;
|
|
}
|
|
|
|
/* Congestion management port init */
|
|
static inline void ecore_init_cmng(const struct cmng_init_input *input_data,
|
|
struct cmng_init *ram_data)
|
|
{
|
|
uint32_t r_param;
|
|
ECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init));
|
|
|
|
ram_data->port.flags = input_data->flags;
|
|
|
|
/*
|
|
* number of bytes transmitted in a rate of 10Gbps
|
|
* in one usec = 1.25KB.
|
|
*/
|
|
r_param = BITS_TO_BYTES(input_data->port_rate);
|
|
ecore_init_max(input_data, r_param, ram_data);
|
|
ecore_init_min(input_data, r_param, ram_data);
|
|
ecore_init_fw_wrr(input_data, r_param, ram_data);
|
|
ecore_init_safc(input_data, ram_data);
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Returns the index of start or end of a specific block stage in ops array*/
|
|
#define BLOCK_OPS_IDX(block, stage, end) \
|
|
(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
|
|
|
|
|
|
#define INITOP_SET 0 /* set the HW directly */
|
|
#define INITOP_CLEAR 1 /* clear the HW directly */
|
|
#define INITOP_INIT 2 /* set the init-value array */
|
|
|
|
/****************************************************************************
|
|
* ILT management
|
|
****************************************************************************/
|
|
struct ilt_line {
|
|
ecore_dma_addr_t page_mapping;
|
|
void *page;
|
|
uint32_t size;
|
|
};
|
|
|
|
struct ilt_client_info {
|
|
uint32_t page_size;
|
|
uint16_t start;
|
|
uint16_t end;
|
|
uint16_t client_num;
|
|
uint16_t flags;
|
|
#define ILT_CLIENT_SKIP_INIT 0x1
|
|
#define ILT_CLIENT_SKIP_MEM 0x2
|
|
};
|
|
|
|
struct ecore_ilt {
|
|
uint32_t start_line;
|
|
struct ilt_line *lines;
|
|
struct ilt_client_info clients[4];
|
|
#define ILT_CLIENT_CDU 0
|
|
#define ILT_CLIENT_QM 1
|
|
#define ILT_CLIENT_SRC 2
|
|
#define ILT_CLIENT_TM 3
|
|
};
|
|
|
|
/****************************************************************************
|
|
* SRC configuration
|
|
****************************************************************************/
|
|
struct src_ent {
|
|
uint8_t opaque[56];
|
|
uint64_t next;
|
|
};
|
|
|
|
/****************************************************************************
|
|
* Parity configuration
|
|
****************************************************************************/
|
|
#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \
|
|
{ \
|
|
block##_REG_##block##_PRTY_MASK, \
|
|
block##_REG_##block##_PRTY_STS_CLR, \
|
|
en_mask, {m1, m1h, m2, m3}, #block \
|
|
}
|
|
|
|
#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \
|
|
{ \
|
|
block##_REG_##block##_PRTY_MASK_0, \
|
|
block##_REG_##block##_PRTY_STS_CLR_0, \
|
|
en_mask, {m1, m1h, m2, m3}, #block"_0" \
|
|
}
|
|
|
|
#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \
|
|
{ \
|
|
block##_REG_##block##_PRTY_MASK_1, \
|
|
block##_REG_##block##_PRTY_STS_CLR_1, \
|
|
en_mask, {m1, m1h, m2, m3}, #block"_1" \
|
|
}
|
|
|
|
static const struct {
|
|
uint32_t mask_addr;
|
|
uint32_t sts_clr_addr;
|
|
uint32_t en_mask; /* Mask to enable parity attentions */
|
|
struct {
|
|
uint32_t e1; /* 57710 */
|
|
uint32_t e1h; /* 57711 */
|
|
uint32_t e2; /* 57712 */
|
|
uint32_t e3; /* 578xx */
|
|
} reg_mask; /* Register mask (all valid bits) */
|
|
char name[8]; /* Block's longest name is 7 characters long
|
|
* (name + suffix)
|
|
*/
|
|
} ecore_blocks_parity_data[] = {
|
|
/* bit 19 masked */
|
|
/* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
|
|
/* bit 5,18,20-31 */
|
|
/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
|
|
/* bit 5 */
|
|
/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
|
|
/* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
|
|
/* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
|
|
|
|
/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
|
|
* want to handle "system kill" flow at the moment.
|
|
*/
|
|
BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,
|
|
0x7ffffff),
|
|
BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
|
|
0xffffffff),
|
|
BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),
|
|
BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),
|
|
BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),
|
|
BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff, 0xffffffff),
|
|
BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xff, 0xffff),
|
|
BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),
|
|
BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
|
|
BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
|
|
BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),
|
|
BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),
|
|
BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),
|
|
{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
|
|
GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
|
|
{0xf, 0xf, 0xf, 0xf}, "UPB"},
|
|
{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
|
|
GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
|
|
{0xf, 0xf, 0xf, 0xf}, "XPB"},
|
|
BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),
|
|
BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),
|
|
BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),
|
|
BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),
|
|
BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),
|
|
BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),
|
|
BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff, 0xff),
|
|
BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),
|
|
BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),
|
|
BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
|
|
BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
|
|
BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
|
|
BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
|
|
BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
|
|
BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
|
|
BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
|
|
BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
|
|
BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
|
|
0xffffffff),
|
|
BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
|
|
BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
|
|
0xffffffff),
|
|
BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
|
|
BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
|
|
0xffffffff),
|
|
BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
|
|
BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
|
|
0xffffffff),
|
|
BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
|
|
};
|
|
|
|
|
|
/* [28] MCP Latched rom_parity
|
|
* [29] MCP Latched ump_rx_parity
|
|
* [30] MCP Latched ump_tx_parity
|
|
* [31] MCP Latched scpad_parity
|
|
*/
|
|
#define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \
|
|
(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
|
|
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
|
|
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
|
|
|
|
#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
|
|
(MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \
|
|
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
|
|
|
|
/* Below registers control the MCP parity attention output. When
|
|
* MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
|
|
* enabled, when cleared - disabled.
|
|
*/
|
|
static const struct {
|
|
uint32_t addr;
|
|
uint32_t bits;
|
|
} mcp_attn_ctl_regs[] = {
|
|
{ MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
|
|
MISC_AEU_ENABLE_MCP_PRTY_BITS },
|
|
{ MISC_REG_AEU_ENABLE4_NIG_0,
|
|
MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
|
|
{ MISC_REG_AEU_ENABLE4_PXP_0,
|
|
MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
|
|
{ MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
|
|
MISC_AEU_ENABLE_MCP_PRTY_BITS },
|
|
{ MISC_REG_AEU_ENABLE4_NIG_1,
|
|
MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
|
|
{ MISC_REG_AEU_ENABLE4_PXP_1,
|
|
MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }
|
|
};
|
|
|
|
static inline void ecore_set_mcp_parity(struct bxe_softc *sc, uint8_t enable)
|
|
{
|
|
int i;
|
|
uint32_t reg_val;
|
|
|
|
for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
|
|
reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr);
|
|
|
|
if (enable)
|
|
reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */
|
|
else
|
|
reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */
|
|
|
|
REG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val);
|
|
}
|
|
}
|
|
|
|
static inline uint32_t ecore_parity_reg_mask(struct bxe_softc *sc, int idx)
|
|
{
|
|
if (CHIP_IS_E1(sc))
|
|
return ecore_blocks_parity_data[idx].reg_mask.e1;
|
|
else if (CHIP_IS_E1H(sc))
|
|
return ecore_blocks_parity_data[idx].reg_mask.e1h;
|
|
else if (CHIP_IS_E2(sc))
|
|
return ecore_blocks_parity_data[idx].reg_mask.e2;
|
|
else /* CHIP_IS_E3 */
|
|
return ecore_blocks_parity_data[idx].reg_mask.e3;
|
|
}
|
|
|
|
static inline void ecore_disable_blocks_parity(struct bxe_softc *sc)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
|
|
uint32_t dis_mask = ecore_parity_reg_mask(sc, i);
|
|
|
|
if (dis_mask) {
|
|
REG_WR(sc, ecore_blocks_parity_data[i].mask_addr,
|
|
dis_mask);
|
|
ECORE_MSG(sc, "Setting parity mask "
|
|
"for %s to\t\t0x%x\n",
|
|
ecore_blocks_parity_data[i].name, dis_mask);
|
|
}
|
|
}
|
|
|
|
/* Disable MCP parity attentions */
|
|
ecore_set_mcp_parity(sc, FALSE);
|
|
}
|
|
|
|
/**
|
|
* Clear the parity error status registers.
|
|
*/
|
|
static inline void ecore_clear_blocks_parity(struct bxe_softc *sc)
|
|
{
|
|
int i;
|
|
uint32_t reg_val, mcp_aeu_bits =
|
|
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
|
|
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
|
|
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
|
|
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
|
|
|
|
/* Clear SEM_FAST parities */
|
|
REG_WR(sc, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
|
|
REG_WR(sc, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
|
|
REG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
|
|
REG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
|
|
|
|
for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
|
|
uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
|
|
|
|
if (reg_mask) {
|
|
reg_val = REG_RD(sc, ecore_blocks_parity_data[i].
|
|
sts_clr_addr);
|
|
if (reg_val & reg_mask)
|
|
ECORE_MSG(sc,
|
|
"Parity errors in %s: 0x%x\n",
|
|
ecore_blocks_parity_data[i].name,
|
|
reg_val & reg_mask);
|
|
}
|
|
}
|
|
|
|
/* Check if there were parity attentions in MCP */
|
|
reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP);
|
|
if (reg_val & mcp_aeu_bits)
|
|
ECORE_MSG(sc, "Parity error in MCP: 0x%x\n",
|
|
reg_val & mcp_aeu_bits);
|
|
|
|
/* Clear parity attentions in MCP:
|
|
* [7] clears Latched rom_parity
|
|
* [8] clears Latched ump_rx_parity
|
|
* [9] clears Latched ump_tx_parity
|
|
* [10] clears Latched scpad_parity (both ports)
|
|
*/
|
|
REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
|
|
}
|
|
|
|
static inline void ecore_enable_blocks_parity(struct bxe_softc *sc)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
|
|
uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
|
|
|
|
if (reg_mask)
|
|
REG_WR(sc, ecore_blocks_parity_data[i].mask_addr,
|
|
ecore_blocks_parity_data[i].en_mask & reg_mask);
|
|
}
|
|
|
|
/* Enable MCP parity attentions */
|
|
ecore_set_mcp_parity(sc, TRUE);
|
|
}
|
|
|
|
|
|
#endif /* ECORE_INIT_H */
|
|
|