4fa8db5df0
it's probed first. The PowerPC platform code deals with everything. As such, probe devices in order of their location in the memory map. o Refactor the ocpbus_alloc_resource for readability and make sure we set the RID in the resource as per the new convention.
597 lines
15 KiB
C
597 lines
15 KiB
C
/*-
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* Copyright 2006 by Juniper Networks. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/ktr.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/malloc.h>
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#include <machine/spr.h>
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#include <machine/pio.h>
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#include <machine/ocpbus.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/vmparam.h>
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#include <machine/bootinfo.h>
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#include <powerpc/mpc85xx/ocpbus.h>
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#include "pic_if.h"
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extern struct bus_space bs_be_tag;
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struct ocpbus_softc {
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struct rman sc_mem;
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struct rman sc_irq;
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};
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struct ocp_devinfo {
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int ocp_devtype;
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int ocp_unit;
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};
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static int ocpbus_probe(device_t);
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static int ocpbus_attach(device_t);
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static int ocpbus_shutdown(device_t);
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static int ocpbus_get_resource(device_t, device_t, int, int, u_long *,
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u_long *);
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static struct resource *ocpbus_alloc_resource(device_t, device_t, int, int *,
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u_long, u_long, u_long, u_int);
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static int ocpbus_print_child(device_t, device_t);
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static int ocpbus_release_resource(device_t, device_t, int, int,
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struct resource *);
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static int ocpbus_read_ivar(device_t, device_t, int, uintptr_t *);
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static int ocpbus_setup_intr(device_t, device_t, struct resource *, int,
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driver_filter_t *, driver_intr_t *, void *, void **);
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static int ocpbus_teardown_intr(device_t, device_t, struct resource *, void *);
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/*
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* Bus interface definition
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*/
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static device_method_t ocpbus_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ocpbus_probe),
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DEVMETHOD(device_attach, ocpbus_attach),
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DEVMETHOD(device_shutdown, ocpbus_shutdown),
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/* Bus interface */
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DEVMETHOD(bus_print_child, ocpbus_print_child),
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DEVMETHOD(bus_read_ivar, ocpbus_read_ivar),
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DEVMETHOD(bus_setup_intr, ocpbus_setup_intr),
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DEVMETHOD(bus_teardown_intr, ocpbus_teardown_intr),
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DEVMETHOD(bus_get_resource, ocpbus_get_resource),
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DEVMETHOD(bus_alloc_resource, ocpbus_alloc_resource),
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DEVMETHOD(bus_release_resource, ocpbus_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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{ 0, 0 }
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};
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static driver_t ocpbus_driver = {
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"ocpbus",
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ocpbus_methods,
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sizeof(struct ocpbus_softc)
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};
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devclass_t ocpbus_devclass;
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DRIVER_MODULE(ocpbus, nexus, ocpbus_driver, ocpbus_devclass, 0, 0);
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static device_t
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ocpbus_mk_child(device_t dev, int type, int unit)
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{
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struct ocp_devinfo *dinfo;
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device_t child;
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child = device_add_child(dev, NULL, -1);
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if (child == NULL) {
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device_printf(dev, "could not add child device\n");
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return (NULL);
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}
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dinfo = malloc(sizeof(struct ocp_devinfo), M_DEVBUF, M_WAITOK|M_ZERO);
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dinfo->ocp_devtype = type;
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dinfo->ocp_unit = unit;
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device_set_ivars(child, dinfo);
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return (child);
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}
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static int
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ocpbus_write_law(int trgt, int type, u_long *startp, u_long *countp)
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{
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u_long addr, size;
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int i;
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uint32_t bar, sr;
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switch (type) {
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case SYS_RES_MEMORY:
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switch (trgt) {
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case OCP85XX_TGTIF_PCI0:
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addr = 0x80000000;
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size = 0x10000000;
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break;
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case OCP85XX_TGTIF_PCI1:
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addr = 0x90000000;
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size = 0x10000000;
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break;
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case OCP85XX_TGTIF_PCI2:
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addr = 0xA0000000;
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size = 0x10000000;
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break;
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default:
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return (EINVAL);
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}
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break;
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case SYS_RES_IOPORT:
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switch (trgt) {
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case OCP85XX_TGTIF_PCI0:
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addr = 0xff000000;
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size = 0x00010000;
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break;
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case OCP85XX_TGTIF_PCI1:
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addr = 0xff010000;
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size = 0x00010000;
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break;
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case OCP85XX_TGTIF_PCI2:
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addr = 0xff020000;
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size = 0x00010000;
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break;
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default:
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return (EINVAL);
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}
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break;
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default:
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return (EINVAL);
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}
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*startp = addr;
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*countp = size;
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/* Program the LAWs for this memory range. */
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bar = addr >> 12;
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sr = 0x80000000 | (trgt << 20) | (ffsl(size) - 2);
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/* Check if already programmed. */
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for (i = 0; i < 8; i++) {
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if (sr == in32(OCP85XX_LAWSR(i)) &&
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bar == in32(OCP85XX_LAWBAR(i)))
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return (0);
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}
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/* Find an unused access window .*/
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for (i = 0; i < 8; i++) {
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if ((in32(OCP85XX_LAWSR(i)) & 0x80000000) == 0)
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break;
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}
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if (i == 8)
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return (ENOSPC);
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out32(OCP85XX_LAWBAR(i), bar);
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out32(OCP85XX_LAWSR(i), sr);
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return (0);
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}
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static int
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ocpbus_probe (device_t dev)
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{
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device_set_desc(dev, "On-Chip Peripherals bus");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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ocpbus_attach (device_t dev)
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{
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struct ocpbus_softc *sc;
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int error, i;
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uint32_t sr;
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u_long start, end;
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sc = device_get_softc(dev);
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ocpbus_mk_child(dev, OCPBUS_DEVTYPE_I2C, 0);
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ocpbus_mk_child(dev, OCPBUS_DEVTYPE_I2C, 1);
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ocpbus_mk_child(dev, OCPBUS_DEVTYPE_UART, 0);
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ocpbus_mk_child(dev, OCPBUS_DEVTYPE_UART, 1);
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ocpbus_mk_child(dev, OCPBUS_DEVTYPE_LBC, 0);
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ocpbus_mk_child(dev, OCPBUS_DEVTYPE_PCIB, 0);
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ocpbus_mk_child(dev, OCPBUS_DEVTYPE_PCIB, 1);
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ocpbus_mk_child(dev, OCPBUS_DEVTYPE_PCIB, 2);
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ocpbus_mk_child(dev, OCPBUS_DEVTYPE_TSEC, 0);
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ocpbus_mk_child(dev, OCPBUS_DEVTYPE_TSEC, 1);
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ocpbus_mk_child(dev, OCPBUS_DEVTYPE_TSEC, 2);
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ocpbus_mk_child(dev, OCPBUS_DEVTYPE_TSEC, 3);
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ocpbus_mk_child(dev, OCPBUS_DEVTYPE_PIC, 0);
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ocpbus_mk_child(dev, OCPBUS_DEVTYPE_QUICC, 0);
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/* Set up IRQ rman */
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start = 0;
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end = INTR_VECTORS - 1;
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sc->sc_irq.rm_start = start;
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sc->sc_irq.rm_end = end;
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sc->sc_irq.rm_type = RMAN_ARRAY;
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sc->sc_irq.rm_descr = "Interrupt request lines";
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if (rman_init(&sc->sc_irq) ||
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rman_manage_region(&sc->sc_irq, start, end))
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panic("ocpbus_attach IRQ rman");
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/* Set up I/O mem rman */
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sc->sc_mem.rm_type = RMAN_ARRAY;
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sc->sc_mem.rm_descr = "OCPBus Device Memory";
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error = rman_init(&sc->sc_mem);
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if (error) {
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device_printf(dev, "rman_init() failed. error = %d\n", error);
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return (error);
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}
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error = rman_manage_region(&sc->sc_mem, CCSRBAR_VA,
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CCSRBAR_VA + CCSRBAR_SIZE - 1);
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if (error) {
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device_printf(dev, "rman_manage_region() failed. error = %d\n",
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error);
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return (error);
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}
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/* Clear local access windows. */
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for (i = 0; i < 8; i++) {
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sr = in32(OCP85XX_LAWSR(i));
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if ((sr & 0x80000000) == 0)
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continue;
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if ((sr & 0x00f00000) == 0x00f00000)
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continue;
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out32(OCP85XX_LAWSR(i), sr & 0x7fffffff);
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}
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if (bootverbose)
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device_printf(dev, "PORDEVSR=%08x, PORDEVSR2=%08x\n",
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in32(OCP85XX_PORDEVSR), in32(OCP85XX_PORDEVSR2));
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return (bus_generic_attach(dev));
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}
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static int
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ocpbus_shutdown(device_t dev)
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{
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return(0);
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}
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struct ocp_resource {
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int sr_devtype;
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int sr_unit;
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int sr_resource;
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int sr_rid;
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int sr_offset;
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int sr_size;
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};
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const struct ocp_resource mpc8555_resources[] = {
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{OCPBUS_DEVTYPE_PIC, 0, SYS_RES_MEMORY, 0, OCP85XX_OPENPIC_OFF,
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OCP85XX_OPENPIC_SIZE},
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{OCPBUS_DEVTYPE_QUICC, 0, SYS_RES_MEMORY, 0, OCP85XX_QUICC_OFF,
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OCP85XX_QUICC_SIZE},
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{OCPBUS_DEVTYPE_QUICC, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(30), 1},
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{OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_MEMORY, 0, OCP85XX_TSEC0_OFF,
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OCP85XX_TSEC_SIZE},
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{OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(13), 1},
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{OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 1, PIC_IRQ_INT(14), 1},
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{OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 2, PIC_IRQ_INT(18), 1},
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{OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_MEMORY, 0, OCP85XX_TSEC1_OFF,
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OCP85XX_TSEC_SIZE},
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{OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 0, PIC_IRQ_INT(19), 1},
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{OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 1, PIC_IRQ_INT(20), 1},
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{OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 2, PIC_IRQ_INT(24), 1},
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{OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_MEMORY, 0, OCP85XX_TSEC2_OFF,
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OCP85XX_TSEC_SIZE},
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{OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 0, PIC_IRQ_INT(15), 1},
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{OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 1, PIC_IRQ_INT(16), 1},
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{OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 2, PIC_IRQ_INT(17), 1},
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{OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_MEMORY, 0, OCP85XX_TSEC3_OFF,
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OCP85XX_TSEC_SIZE},
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{OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 0, PIC_IRQ_INT(21), 1},
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{OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 1, PIC_IRQ_INT(22), 1},
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{OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 2, PIC_IRQ_INT(23), 1},
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{OCPBUS_DEVTYPE_UART, 0, SYS_RES_MEMORY, 0, OCP85XX_UART0_OFF,
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OCP85XX_UART_SIZE},
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{OCPBUS_DEVTYPE_UART, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(26), 1},
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{OCPBUS_DEVTYPE_UART, 1, SYS_RES_MEMORY, 0, OCP85XX_UART1_OFF,
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OCP85XX_UART_SIZE},
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{OCPBUS_DEVTYPE_UART, 1, SYS_RES_IRQ, 0, PIC_IRQ_INT(26), 1},
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{OCPBUS_DEVTYPE_PCIB, 0, SYS_RES_MEMORY, 0, OCP85XX_PCI0_OFF,
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OCP85XX_PCI_SIZE},
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{OCPBUS_DEVTYPE_PCIB, 0, SYS_RES_MEMORY, 1, 0, OCP85XX_TGTIF_PCI0},
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{OCPBUS_DEVTYPE_PCIB, 0, SYS_RES_IOPORT, 1, 0, OCP85XX_TGTIF_PCI0},
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{OCPBUS_DEVTYPE_PCIB, 1, SYS_RES_MEMORY, 0, OCP85XX_PCI1_OFF,
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OCP85XX_PCI_SIZE},
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{OCPBUS_DEVTYPE_PCIB, 1, SYS_RES_MEMORY, 1, 0, OCP85XX_TGTIF_PCI1},
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{OCPBUS_DEVTYPE_PCIB, 1, SYS_RES_IOPORT, 1, 0, OCP85XX_TGTIF_PCI1},
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{OCPBUS_DEVTYPE_PCIB, 2, SYS_RES_MEMORY, 0, OCP85XX_PCI2_OFF,
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OCP85XX_PCI_SIZE},
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{OCPBUS_DEVTYPE_PCIB, 2, SYS_RES_MEMORY, 1, 0, OCP85XX_TGTIF_PCI2},
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{OCPBUS_DEVTYPE_PCIB, 2, SYS_RES_IOPORT, 1, 0, OCP85XX_TGTIF_PCI2},
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{OCPBUS_DEVTYPE_LBC, 0, SYS_RES_MEMORY, 0, OCP85XX_LBC_OFF,
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OCP85XX_LBC_SIZE},
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{OCPBUS_DEVTYPE_LBC, 0, SYS_RES_MEMORY, 1, 0, OCP85XX_TGTIF_LBC},
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{OCPBUS_DEVTYPE_I2C, 0, SYS_RES_MEMORY, 0, OCP85XX_I2C0_OFF,
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OCP85XX_I2C_SIZE},
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{OCPBUS_DEVTYPE_I2C, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(27), 1},
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{OCPBUS_DEVTYPE_I2C, 1, SYS_RES_MEMORY, 0, OCP85XX_I2C1_OFF,
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OCP85XX_I2C_SIZE},
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{OCPBUS_DEVTYPE_I2C, 1, SYS_RES_IRQ, 0, PIC_IRQ_INT(27), 1},
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{0}
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};
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static int
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ocpbus_get_resource(device_t dev, device_t child, int type, int rid,
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u_long *startp, u_long *countp)
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{
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const struct ocp_resource *res;
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struct ocp_devinfo *dinfo;
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u_long start = 0, count = 0;
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int error;
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dinfo = device_get_ivars(child);
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/*
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* Lookup the correct values.
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*/
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res = mpc8555_resources;
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for (; res->sr_devtype; res++) {
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if (res->sr_devtype != dinfo->ocp_devtype)
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continue;
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if (res->sr_unit != dinfo->ocp_unit)
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continue;
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if (res->sr_rid != rid)
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continue;
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if (res->sr_resource != type)
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continue;
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if (res->sr_offset != 0) {
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error = 0;
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switch (type) {
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case SYS_RES_MEMORY:
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start = res->sr_offset + CCSRBAR_VA;
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break;
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case SYS_RES_IRQ:
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start = res->sr_offset;
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break;
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default:
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error = EINVAL;
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break;
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}
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count = res->sr_size;
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} else
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error = ocpbus_write_law(res->sr_size, type, &start,
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&count);
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if (!error) {
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if (startp != NULL)
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*startp = start;
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if (countp != NULL)
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*countp = count;
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}
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return (error);
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}
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return (ENOENT);
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}
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static struct resource *
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ocpbus_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct ocpbus_softc *sc;
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struct resource *rv;
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int error;
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sc = device_get_softc(dev);
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switch (type) {
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case SYS_RES_IRQ:
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if (start == 0ul && end == ~0ul) {
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error = ocpbus_get_resource(dev, child, type, *rid,
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&start, &count);
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if (error)
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return (NULL);
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}
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/*
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* ISA interrupts (IRQ 0-15) are remapped by the
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* PCI driver. Make sure this happened.
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*/
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if (start < PIC_IRQ_START)
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return (NULL);
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rv = rman_reserve_resource(&sc->sc_irq, start - PIC_IRQ_START,
|
|
start - PIC_IRQ_START + count - 1, count, flags, child);
|
|
if (rv == NULL)
|
|
return (NULL);
|
|
break;
|
|
|
|
case SYS_RES_MEMORY:
|
|
if (start != 0ul || end != ~0ul)
|
|
return (NULL);
|
|
|
|
error = ocpbus_get_resource(dev, child, type, *rid, &start,
|
|
&count);
|
|
if (error)
|
|
return (NULL);
|
|
|
|
rv = rman_reserve_resource(&sc->sc_mem, start,
|
|
start + count - 1, count, flags, child);
|
|
if (rv == NULL)
|
|
return (NULL);
|
|
|
|
rman_set_bustag(rv, &bs_be_tag);
|
|
rman_set_bushandle(rv, rman_get_start(rv));
|
|
break;
|
|
|
|
default:
|
|
return (NULL);
|
|
}
|
|
|
|
rman_set_rid(rv, *rid);
|
|
return (rv);
|
|
}
|
|
|
|
static int
|
|
ocpbus_print_child(device_t dev, device_t child)
|
|
{
|
|
u_long size, start;
|
|
int error, retval, rid;
|
|
|
|
retval = bus_print_child_header(dev, child);
|
|
|
|
rid = 0;
|
|
while (1) {
|
|
error = ocpbus_get_resource(dev, child, SYS_RES_MEMORY, rid,
|
|
&start, &size);
|
|
if (error)
|
|
break;
|
|
retval += (rid == 0) ? printf(" iomem ") : printf(",");
|
|
retval += printf("%#lx", start);
|
|
if (size > 1)
|
|
retval += printf("-%#lx", start + size - 1);
|
|
rid++;
|
|
}
|
|
|
|
/*
|
|
* The SYS_RES_IOPORT resource of the PCIB has rid 1 because the
|
|
* the SYS_RES_MEMORY resource related to the decoding window also
|
|
* has rid 1. This is friendlier for the PCIB child...
|
|
*/
|
|
rid = 1;
|
|
while (1) {
|
|
error = ocpbus_get_resource(dev, child, SYS_RES_IOPORT, rid,
|
|
&start, &size);
|
|
if (error)
|
|
break;
|
|
retval += (rid == 1) ? printf(" ioport ") : printf(",");
|
|
retval += printf("%#lx", start);
|
|
if (size > 1)
|
|
retval += printf("-%#lx", start + size - 1);
|
|
rid++;
|
|
}
|
|
|
|
rid = 0;
|
|
while (1) {
|
|
error = ocpbus_get_resource(dev, child, SYS_RES_IRQ, rid,
|
|
&start, &size);
|
|
if (error)
|
|
break;
|
|
retval += (rid == 0) ? printf(" irq ") : printf(",");
|
|
retval += printf("%ld", start);
|
|
rid++;
|
|
}
|
|
|
|
retval += bus_print_child_footer(dev, child);
|
|
return (retval);
|
|
}
|
|
|
|
static int
|
|
ocpbus_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
|
|
{
|
|
struct ocp_devinfo *dinfo;
|
|
|
|
if (device_get_parent(child) != dev)
|
|
return (EINVAL);
|
|
|
|
dinfo = device_get_ivars(child);
|
|
|
|
switch (index) {
|
|
case OCPBUS_IVAR_CLOCK:
|
|
*result = bootinfo->bi_bus_clk;
|
|
return (0);
|
|
case OCPBUS_IVAR_DEVTYPE:
|
|
*result = dinfo->ocp_devtype;
|
|
return (0);
|
|
case OCPBUS_IVAR_HWUNIT:
|
|
*result = dinfo->ocp_unit;
|
|
return (0);
|
|
}
|
|
|
|
return (EINVAL);
|
|
}
|
|
|
|
static int
|
|
ocpbus_release_resource(device_t dev, device_t child, int type, int rid,
|
|
struct resource *res)
|
|
{
|
|
|
|
return (rman_release_resource(res));
|
|
}
|
|
|
|
static int
|
|
ocpbus_setup_intr(device_t dev, device_t child, struct resource *res, int flags,
|
|
driver_filter_t *filter, driver_intr_t *ihand, void *arg, void **cookiep)
|
|
{
|
|
int error;
|
|
|
|
if (res == NULL)
|
|
panic("ocpbus_setup_intr: NULL irq resource!");
|
|
|
|
*cookiep = 0;
|
|
if ((rman_get_flags(res) & RF_SHAREABLE) == 0)
|
|
flags |= INTR_EXCL;
|
|
|
|
/*
|
|
* We depend here on rman_activate_resource() being idempotent.
|
|
*/
|
|
error = rman_activate_resource(res);
|
|
if (error)
|
|
return (error);
|
|
|
|
error = powerpc_setup_intr(device_get_nameunit(child),
|
|
rman_get_start(res), filter, ihand, arg, flags, cookiep);
|
|
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
ocpbus_teardown_intr(device_t dev, device_t child, struct resource *res,
|
|
void *cookie)
|
|
{
|
|
|
|
return (powerpc_teardown_intr(cookie));
|
|
}
|