508 lines
11 KiB
ArmAsm
508 lines
11 KiB
ArmAsm
/*-
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* Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "assym.s"
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#include <machine/param.h>
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#include <machine/asm.h>
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#include <machine/spr.h>
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#include <machine/psl.h>
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#include <machine/pte.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#include <machine/tlb.h>
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#include <machine/bootinfo.h>
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#define TMPSTACKSZ 16384
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.text
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.globl btext
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btext:
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/*
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* This symbol is here for the benefit of kvm_mkdb, and is supposed to
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* mark the start of kernel text.
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*/
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.globl kernel_text
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kernel_text:
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/*
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* Startup entry. Note, this must be the first thing in the text segment!
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*/
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.text
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.globl __start
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__start:
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/*
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* Assumption on a boot loader:
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* - system memory starts from physical address 0
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* - kernel is loaded at 16MB boundary
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* - it's mapped by a single TBL1 entry
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* - TLB1 mapping is 1:1 pa to va
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* - all PID registers are set to the same value
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*
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* Loader register use:
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* r1 : stack pointer
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* r3 : metadata pointer
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*
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* We rearrange the TLB1 layout as follows:
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* - find AS and entry kernel started in
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* - make sure it's protected, ivalidate other entries
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* - create temp entry in the second AS (make sure it's not TLB[15])
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* - switch to temp mapping
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* - map 16MB of RAM in TLB1[15]
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* - use AS=1, set EPN to KERNBASE and RPN to kernel load address
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* - switch to to TLB1[15] mapping
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* - invalidate temp mapping
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*
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* locore register use:
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* r1 : stack pointer
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* r2 : unused
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* r3 : kernel_text
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* r4 : _end
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* r5 : metadata pointer
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* r6-r9 : unused
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* r10 : entry we started in
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* r11 : temp entry
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* r12 : AS we started in
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* r13-r31 : auxiliary registers
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*/
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/*
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* Move metadata ptr to r5
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*/
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mr %r5, %r3
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/*
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* Initial cleanup
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*/
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li %r16, 0x200 /* Keep debug exceptions for CodeWarrior. */
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mtmsr %r16
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isync
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#if 0
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mtspr SPR_HID0, %r16
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isync
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msync
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mtspr SPR_HID1, %r16
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isync
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#endif
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/* Issue INV_ALL Invalidate on TLB0 */
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li %r16, 0x04
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tlbivax 0, %r16
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isync
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msync
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/*
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* Use tblsx to locate the TLB1 entry that maps kernel code
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*/
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bl 1f /* Current address */
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1: mflr %r15
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/* Find entry that maps current address */
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mfspr %r17, SPR_PID0
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slwi %r17, %r17, MAS6_SPID0_SHIFT
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mtspr SPR_MAS6, %r17
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isync
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tlbsx 0, %r15
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/* Copy entry number to r10 */
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mfspr %r17, SPR_MAS0
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rlwinm %r10, %r17, 16, 28, 31
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/* Invalidate TLB1, skipping our entry. */
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mfspr %r17, SPR_TLB1CFG /* Get number of entries */
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andi. %r17, %r17, TLBCFG_NENTRY_MASK@l
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li %r16, 0 /* Start from Entry 0 */
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2: lis %r15, MAS0_TLBSEL1@h /* Select TLB1 */
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rlwimi %r15, %r16, 16, 12, 15
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mtspr SPR_MAS0, %r15
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isync
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tlbre
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mfspr %r15, SPR_MAS1
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cmpw %r16, %r10
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beq 3f
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/* Clear VALID and IPROT bits for other entries */
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rlwinm %r15, %r15, 0, 2, 31
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mtspr SPR_MAS1, %r15
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isync
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tlbwe
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isync
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msync
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3: addi %r16, %r16, 1
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cmpw %r16, %r17 /* Check if this is the last entry */
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bne 2b
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/*
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* Create temporary mapping in the other Address Space
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*/
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lis %r17, MAS0_TLBSEL1@h /* Select TLB1 */
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rlwimi %r17, %r10, 16, 12, 15 /* Select our entry */
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mtspr SPR_MAS0, %r17
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isync
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tlbre /* Read it in */
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/* Prepare and write temp entry */
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lis %r17, MAS0_TLBSEL1@h /* Select TLB1 */
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addi %r11, %r10, 0x1 /* Use next entry. */
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rlwimi %r17, %r11, 16, 12, 15 /* Select temp entry */
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mtspr SPR_MAS0, %r17
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isync
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mfspr %r16, SPR_MAS1
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li %r15, 1 /* AS 1 */
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rlwimi %r16, %r15, 12, 19, 19
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mtspr SPR_MAS1, %r16
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li %r17, 0
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rlwimi %r16, %r17, 0, 8, 15 /* Global mapping, TID=0 */
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isync
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tlbwe
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isync
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msync
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mfmsr %r16
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ori %r16, %r16, 0x30 /* Switch to AS 1. */
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bl 4f /* Find current execution address */
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4: mflr %r15
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addi %r15, %r15, 20 /* Increment to instruction after rfi */
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mtspr SPR_SRR0, %r15
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mtspr SPR_SRR1, %r16
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rfi /* Switch context */
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/*
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* Invalidate initial entry
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*/
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mr %r22, %r10
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bl tlb1_inval_entry
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/*
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* Setup final mapping in TLB1[1] and switch to it
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*/
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/* Final kernel mapping, map in 16 MB of RAM */
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lis %r16, MAS0_TLBSEL1@h /* Select TLB1 */
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li %r17, 1 /* Entry 1 */
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rlwimi %r16, %r17, 16, 12, 15
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mtspr SPR_MAS0, %r16
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isync
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li %r16, (TLB_SIZE_16M << MAS1_TSIZE_SHIFT)@l
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oris %r16, %r16, (MAS1_VALID | MAS1_IPROT)@h
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mtspr SPR_MAS1, %r16
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isync
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lis %r19, KERNBASE@h
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ori %r19, %r19, KERNBASE@l
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mtspr SPR_MAS2, %r19 /* Set final EPN, clear WIMG */
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isync
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bl 5f
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5: mflr %r16 /* Use current address */
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lis %r18, 0xff00 /* 16MB alignment mask */
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and %r16, %r16, %r18
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mr %r25, %r16 /* Copy kernel load address */
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ori %r16, %r16, (MAS3_SX | MAS3_SW | MAS3_SR)@l
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mtspr SPR_MAS3, %r16 /* Set RPN and protection */
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isync
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tlbwe
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isync
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msync
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/* Switch to the above TLB1[1] mapping */
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lis %r18, 0x00ff /* 16MB offset mask */
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ori %r18, %r18, 0xffff
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bl 6f
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6: mflr %r20 /* Use current address */
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and %r20, %r20, %r18 /* Offset from kernel load address */
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add %r20, %r20, %r19 /* Move to kernel virtual address */
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addi %r20, %r20, 32 /* Increment to instr. after rfi */
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li %r21, 0x200
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mtspr SPR_SRR0, %r20
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mtspr SPR_SRR1, %r21
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rfi
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/* Save kernel load address for later use */
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lis %r24, kernload@ha
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addi %r24, %r24, kernload@l
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stw %r25, 0(%r24)
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/*
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* Invalidate temp mapping
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*/
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mr %r22, %r11
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bl tlb1_inval_entry
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/*
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* Setup a temporary stack
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*/
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lis %r1, tmpstack@ha
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addi %r1, %r1, tmpstack@l
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addi %r1, %r1, (TMPSTACKSZ - 8)
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/*
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* Intialise exception vector offsets
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*/
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bl ivor_setup
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/*
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* Jump to system initialization code
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*
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* Setup first two arguments for e500_init, metadata (r5) is already in place.
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*/
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lis %r3, kernel_text@ha
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addi %r3, %r3, kernel_text@l
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lis %r4, _end@ha
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addi %r4, %r4, _end@l
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bl e500_init
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/* Switch to thread0.td_kstack */
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mr %r1, %r3
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li %r3, 0
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stw %r3, 0(%r1)
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bl mi_startup /* Machine independet part, does not return */
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/************************************************************************/
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/* locore subroutines */
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/************************************************************************/
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tlb1_inval_entry:
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lis %r17, MAS0_TLBSEL1@h /* Select TLB1 */
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rlwimi %r17, %r22, 16, 12, 15 /* Select our entry */
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mtspr SPR_MAS0, %r17
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isync
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tlbre /* Read it in */
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li %r16, 0
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mtspr SPR_MAS1, %r16
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isync
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tlbwe
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isync
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msync
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blr
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ivor_setup:
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/* Set base address of interrupt handler routines */
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lis %r21, interrupt_vector_base@h
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mtspr SPR_IVPR, %r21
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/* Assign interrupt handler routines offsets */
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li %r21, int_critical_input@l
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mtspr SPR_IVOR0, %r21
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li %r21, int_machine_check@l
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mtspr SPR_IVOR1, %r21
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li %r21, int_data_storage@l
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mtspr SPR_IVOR2, %r21
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li %r21, int_instr_storage@l
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mtspr SPR_IVOR3, %r21
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li %r21, int_external_input@l
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mtspr SPR_IVOR4, %r21
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li %r21, int_alignment@l
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mtspr SPR_IVOR5, %r21
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li %r21, int_program@l
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mtspr SPR_IVOR6, %r21
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li %r21, int_syscall@l
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mtspr SPR_IVOR8, %r21
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li %r21, int_decrementer@l
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mtspr SPR_IVOR10, %r21
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li %r21, int_fixed_interval_timer@l
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mtspr SPR_IVOR11, %r21
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li %r21, int_watchdog@l
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mtspr SPR_IVOR12, %r21
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li %r21, int_data_tlb_error@l
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mtspr SPR_IVOR13, %r21
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li %r21, int_inst_tlb_error@l
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mtspr SPR_IVOR14, %r21
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li %r21, int_debug@l
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mtspr SPR_IVOR15, %r21
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blr
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/*
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* void tlb1_inval_va(vm_offset_t va)
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*
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* r3 - va to invalidate
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*/
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ENTRY(tlb1_inval_va)
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/* EA mask */
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lis %r6, 0xffff
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ori %r6, %r6, 0xf000
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and %r3, %r3, %r6
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/* Select TLB1 */
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ori %r3, %r3, 0x08
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isync
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tlbivax 0, %r3
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isync
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msync
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blr
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/*
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* void tlb0_inval_va(vm_offset_t va)
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*
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* r3 - va to invalidate
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*/
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ENTRY(tlb0_inval_va)
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/* EA mask, this also clears TLBSEL, selecting TLB0 */
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lis %r6, 0xffff
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ori %r6, %r6, 0xf000
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and %r3, %r3, %r6
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isync
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tlbivax 0, %r3
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isync
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msync
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blr
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/*
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* Cache disable/enable/inval sequences according
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* to section 2.16 of E500CORE RM.
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*/
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ENTRY(dcache_inval)
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/* Invalidate d-cache */
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mfspr %r3, SPR_L1CSR0
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ori %r3, %r3, (L1CSR0_DCFI | L1CSR0_DCLFR)@l
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msync
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isync
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mtspr SPR_L1CSR0, %r3
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isync
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blr
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ENTRY(dcache_disable)
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/* Disable d-cache */
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mfspr %r3, SPR_L1CSR0
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li %r4, L1CSR0_DCE@l
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not %r4, %r4
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and %r3, %r3, %r4
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msync
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isync
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mtspr SPR_L1CSR0, %r3
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isync
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blr
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ENTRY(dcache_enable)
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/* Enable d-cache */
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mfspr %r3, SPR_L1CSR0
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oris %r3, %r3, (L1CSR0_DCPE | L1CSR0_DCE)@h
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ori %r3, %r3, (L1CSR0_DCPE | L1CSR0_DCE)@l
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msync
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isync
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mtspr SPR_L1CSR0, %r3
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isync
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blr
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ENTRY(icache_inval)
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/* Invalidate i-cache */
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mfspr %r3, SPR_L1CSR1
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ori %r3, %r3, (L1CSR1_ICFI | L1CSR1_ICLFR)@l
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isync
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mtspr SPR_L1CSR1, %r3
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isync
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blr
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ENTRY(icache_disable)
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/* Disable i-cache */
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mfspr %r3, SPR_L1CSR1
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li %r4, L1CSR1_ICE@l
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not %r4, %r4
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and %r3, %r3, %r4
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isync
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mtspr SPR_L1CSR1, %r3
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isync
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blr
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ENTRY(icache_enable)
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/* Enable i-cache */
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mfspr %r3, SPR_L1CSR1
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oris %r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@h
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ori %r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@l
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isync
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mtspr SPR_L1CSR1, %r3
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isync
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blr
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/*
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* int setfault()
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*
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* Similar to setjmp to setup for handling faults on accesses to user memory.
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* Any routine using this may only call bcopy, either the form below,
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* or the (currently used) C code optimized, so it doesn't use any non-volatile
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* registers.
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*/
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.globl setfault
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setfault:
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mflr %r0
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mfsprg0 %r4
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lwz %r4, PC_CURTHREAD(%r4)
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lwz %r4, TD_PCB(%r4)
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stw %r3, PCB_ONFAULT(%r4)
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mfcr %r10
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mfctr %r11
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mfxer %r12
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stw %r0, 0(%r3)
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stw %r1, 4(%r3)
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stw %r2, 8(%r3)
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stmw %r10, 12(%r3) /* store CR, CTR, XER, [r13 .. r31] */
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li %r3, 0 /* return FALSE */
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blr
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/************************************************************************/
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/* Data section */
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/************************************************************************/
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.data
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.align 4
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tmpstack:
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.space TMPSTACKSZ
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/*
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* Compiled KERNBASE locations
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*/
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.globl kernbase
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.set kernbase, KERNBASE
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/*
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* Globals
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*/
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#define INTRCNT_COUNT 256 /* max(HROWPIC_IRQMAX,OPENPIC_IRQMAX) */
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GLOBAL(kernload)
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.long
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GLOBAL(intrnames)
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.space INTRCNT_COUNT * (MAXCOMLEN + 1) * 2
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GLOBAL(eintrnames)
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.align 4
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GLOBAL(intrcnt)
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.space INTRCNT_COUNT * 4 * 2
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GLOBAL(eintrcnt)
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#include <powerpc/booke/trap_subr.S>
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