36c1a37655
Obtained from: Semihalf Authored by: Kornel Duleba <mindal@semihalf.com> Approved by: wma Differential Revision: https://reviews.freebsd.org/D21335
163 lines
4.4 KiB
C
163 lines
4.4 KiB
C
/*-
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* Copyright (c) 2019 Juniper Networks, Inc.
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* Copyright (c) 2019 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/systm.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_bus.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include "mdio_if.h"
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#define BLK_ADDR_REG_OFFSET 0x1f
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#define PLL_AFE1_100MHZ_BLK 0x2100
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#define PLL_CLK_AMP_OFFSET 0x03
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#define PLL_CLK_AMP_2P05V 0x2b18
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struct ns2_pcie_phy_softc {
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uint32_t phy_id;
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};
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static device_probe_t ns2_pcie_phy_fdt_probe;
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static device_attach_t ns2_pcie_phy_fdt_attach;
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static int ns2_pci_phy_init(device_t dev);
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static device_method_t ns2_pcie_phy_fdt_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ns2_pcie_phy_fdt_probe),
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DEVMETHOD(device_attach, ns2_pcie_phy_fdt_attach),
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DEVMETHOD_END
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};
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DEFINE_CLASS_0(ns2_pcie_phy, ns2_pcie_phy_fdt_driver, ns2_pcie_phy_fdt_methods,
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sizeof(struct ns2_pcie_phy_softc));
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static devclass_t ns2_pcie_phy_fdt_devclass;
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static driver_t ns2_pcie_phy_driver = {
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"ns2_pcie_phy",
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ns2_pcie_phy_fdt_methods,
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sizeof(struct ns2_pcie_phy_softc)
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};
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EARLY_DRIVER_MODULE(ns2_pcie_phy, brcm_mdionexus, ns2_pcie_phy_driver,
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ns2_pcie_phy_fdt_devclass, NULL, NULL, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
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static int
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ns2_pci_phy_init(device_t dev)
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{
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struct ns2_pcie_phy_softc *sc;
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int err;
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sc = device_get_softc(dev);
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/* select the AFE 100MHz block page */
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err = MDIO_WRITEREG(device_get_parent(dev), sc->phy_id,
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BLK_ADDR_REG_OFFSET, PLL_AFE1_100MHZ_BLK);
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if (err)
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goto err;
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/* set the 100 MHz reference clock amplitude to 2.05 v */
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err = MDIO_WRITEREG(device_get_parent(dev), sc->phy_id,
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PLL_CLK_AMP_OFFSET, PLL_CLK_AMP_2P05V);
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if (err)
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goto err;
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return 0;
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err:
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device_printf(dev, "Error %d writing to phy\n", err);
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return (err);
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}
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static __inline void
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get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells)
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{
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*addr_cells = 2;
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/* Find address cells if present */
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OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells));
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*size_cells = 2;
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/* Find size cells if present */
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OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells));
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}
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static int
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ns2_pcie_phy_fdt_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "brcm,ns2-pcie-phy"))
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return (ENXIO);
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device_set_desc(dev, "Broadcom NS2 PCIe PHY");
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return (BUS_PROBE_SPECIFIC);
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}
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static int
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ns2_pcie_phy_fdt_attach(device_t dev)
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{
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struct ns2_pcie_phy_softc *sc;
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pcell_t addr_cells, size_cells, buf[2];
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phandle_t node;
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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get_addr_size_cells(OF_parent(node), &addr_cells, &size_cells);
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if ((addr_cells != 1) || (size_cells != 0)) {
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device_printf(dev,
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"Only addr_cells=1 and size_cells=0 are supported\n");
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return (EINVAL);
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}
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if (OF_getencprop(node, "reg", buf, sizeof(pcell_t)) < 0)
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return (ENXIO);
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sc->phy_id = buf[0];
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if (ns2_pci_phy_init(dev) < 0)
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return (EINVAL);
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return (bus_generic_attach(dev));
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}
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