This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs. As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts. This is a preparation patch for NXP LS1046A SoC support. Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351
320 lines
7.7 KiB
C
320 lines
7.7 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2020 Alstom Group.
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* Copyright (c) 2020 Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <arm64/qoriq/clk/qoriq_clkgen.h>
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#include "clkdev_if.h"
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MALLOC_DEFINE(M_QORIQ_CLKGEN, "qoriq_clkgen", "qoriq_clkgen");
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static struct resource_spec qoriq_clkgen_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static const char *qoriq_pll_parents_coreclk[] = {
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QORIQ_CORECLK_NAME
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};
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static const char *qoriq_pll_parents_sysclk[] = {
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QORIQ_SYSCLK_NAME
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};
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static int
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qoriq_clkgen_ofw_mapper(struct clkdom *clkdom, uint32_t ncells,
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phandle_t *cells, struct clknode **clk)
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{
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if (ncells != 2)
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return (EINVAL);
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if (cells[0] > 5)
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return (EINVAL);
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if (cells[0] == QORIQ_TYPE_SYSCLK || cells[0] == QORIQ_TYPE_CORECLK)
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if (cells[1] != 0)
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return (EINVAL);
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*clk = clknode_find_by_id(clkdom, QORIQ_CLK_ID(cells[0], cells[1]));
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if (clk == NULL)
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return (EINVAL);
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return (0);
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}
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static int
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qoriq_clkgen_write_4(device_t dev, bus_addr_t addr, uint32_t val)
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{
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struct qoriq_clkgen_softc *sc;
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sc = device_get_softc(dev);
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if (sc->flags & QORIQ_LITTLE_ENDIAN)
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bus_write_4(sc->res, addr, htole32(val));
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else
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bus_write_4(sc->res, addr, htobe32(val));
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return (0);
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}
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static int
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qoriq_clkgen_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
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{
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struct qoriq_clkgen_softc *sc;
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sc = device_get_softc(dev);
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if (sc->flags & QORIQ_LITTLE_ENDIAN)
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*val = le32toh(bus_read_4(sc->res, addr));
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else
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*val = be32toh(bus_read_4(sc->res, addr));
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return (0);
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}
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static int
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qoriq_clkgen_modify_4(device_t dev, bus_addr_t addr, uint32_t clr,
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uint32_t set)
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{
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struct qoriq_clkgen_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (sc->flags & QORIQ_LITTLE_ENDIAN)
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reg = le32toh(bus_read_4(sc->res, addr));
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else
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reg = be32toh(bus_read_4(sc->res, addr));
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reg &= ~clr;
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reg |= set;
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if (sc->flags & QORIQ_LITTLE_ENDIAN)
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bus_write_4(sc->res, addr, htole32(reg));
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else
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bus_write_4(sc->res, addr, htobe32(reg));
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return (0);
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}
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static void
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qoriq_clkgen_device_lock(device_t dev)
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{
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struct qoriq_clkgen_softc *sc;
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sc = device_get_softc(dev);
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mtx_lock(&sc->mtx);
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}
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static void
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qoriq_clkgen_device_unlock(device_t dev)
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{
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struct qoriq_clkgen_softc *sc;
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sc = device_get_softc(dev);
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mtx_unlock(&sc->mtx);
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}
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static device_method_t qoriq_clkgen_methods[] = {
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DEVMETHOD(clkdev_write_4, qoriq_clkgen_write_4),
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DEVMETHOD(clkdev_read_4, qoriq_clkgen_read_4),
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DEVMETHOD(clkdev_modify_4, qoriq_clkgen_modify_4),
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DEVMETHOD(clkdev_device_lock, qoriq_clkgen_device_lock),
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DEVMETHOD(clkdev_device_unlock, qoriq_clkgen_device_unlock),
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DEVMETHOD_END
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};
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DEFINE_CLASS_0(qoriq_clkgen, qoriq_clkgen_driver, qoriq_clkgen_methods,
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sizeof(struct qoriq_clkgen_softc));
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static int
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qoriq_clkgen_create_sysclk(device_t dev)
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{
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struct qoriq_clkgen_softc *sc;
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struct clk_fixed_def def;
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const char *clkname;
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phandle_t node;
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uint32_t freq;
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clk_t clock;
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int rv;
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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sc->has_coreclk = false;
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memset(&def, 0, sizeof(def));
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rv = OF_getencprop(node, "clock-frequency", &freq, sizeof(freq));
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if (rv > 0) {
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def.clkdef.name = QORIQ_SYSCLK_NAME;
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def.clkdef.id = QORIQ_CLK_ID(QORIQ_TYPE_SYSCLK, 0);
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def.freq = freq;
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rv = clknode_fixed_register(sc->clkdom, &def);
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return (rv);
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} else {
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/*
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* As both sysclk and coreclk need to be accessible from
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* device tree, create internal 1:1 divider nodes.
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*/
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def.clkdef.parent_cnt = 1;
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def.freq = 0;
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def.mult = 1;
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def.div = 1;
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rv = clk_get_by_ofw_name(dev, node, "coreclk", &clock);
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if (rv == 0) {
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def.clkdef.name = QORIQ_CORECLK_NAME;
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clkname = clk_get_name(clock);
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def.clkdef.parent_names = &clkname;
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def.clkdef.id = QORIQ_CLK_ID(QORIQ_TYPE_CORECLK, 0);
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rv = clknode_fixed_register(sc->clkdom, &def);
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if (rv)
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return (rv);
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sc->has_coreclk = true;
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}
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rv = clk_get_by_ofw_name(dev, node, "sysclk", &clock);
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if (rv != 0) {
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rv = clk_get_by_ofw_index(dev, node, 0, &clock);
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if (rv != 0)
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return (rv);
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}
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clkname = clk_get_name(clock);
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def.clkdef.name = QORIQ_SYSCLK_NAME;
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def.clkdef.id = QORIQ_CLK_ID(QORIQ_TYPE_SYSCLK, 0);
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def.clkdef.parent_names = &clkname;
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rv = clknode_fixed_register(sc->clkdom, &def);
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return (rv);
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}
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}
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int
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qoriq_clkgen_attach(device_t dev)
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{
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struct qoriq_clkgen_softc *sc;
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int i, error;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, qoriq_clkgen_spec, &sc->res) != 0) {
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device_printf(dev, "Cannot allocate resources.\n");
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return (ENXIO);
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}
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mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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sc->clkdom = clkdom_create(dev);
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if (sc->clkdom == NULL)
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panic("Cannot create clock domain.\n");
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error = qoriq_clkgen_create_sysclk(dev);
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if (error != 0) {
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device_printf(dev, "Cannot create sysclk.\n");
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return (error);
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}
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sc->pltfrm_pll_def->clkdef.parent_names = qoriq_pll_parents_sysclk;
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sc->pltfrm_pll_def->clkdef.parent_cnt = 1;
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error = qoriq_clk_pll_register(sc->clkdom, sc->pltfrm_pll_def);
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if (error != 0) {
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device_printf(dev, "Cannot create platform PLL.\n");
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return (error);
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}
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for (i = 0; i < sc->cga_pll_num; i++) {
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if (sc->has_coreclk)
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sc->cga_pll[i]->clkdef.parent_names = qoriq_pll_parents_coreclk;
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else
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sc->cga_pll[i]->clkdef.parent_names = qoriq_pll_parents_sysclk;
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sc->cga_pll[i]->clkdef.parent_cnt = 1;
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error = qoriq_clk_pll_register(sc->clkdom, sc->cga_pll[i]);
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if (error != 0) {
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device_printf(dev, "Cannot create CGA PLLs\n.");
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return (error);
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}
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}
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/*
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* Both CMUX and HWACCEL multiplexer nodes can be represented
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* by using built in clk_mux nodes.
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*/
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for (i = 0; i < sc->mux_num; i++) {
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error = clknode_mux_register(sc->clkdom, sc->mux[i]);
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if (error != 0) {
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device_printf(dev, "Cannot create MUX nodes.\n");
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return (error);
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}
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}
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if (sc->init_func != NULL) {
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error = sc->init_func(dev);
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if (error) {
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device_printf(dev, "Clock init function failed.\n");
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return (error);
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}
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}
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clkdom_set_ofw_mapper(sc->clkdom, qoriq_clkgen_ofw_mapper);
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if (clkdom_finit(sc->clkdom) != 0)
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panic("Cannot finalize clock domain initialization.\n");
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if (bootverbose)
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clkdom_dump(sc->clkdom);
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return (0);
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}
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