baf41202ca
Wrappered and enabled by the define BETTER_CLOCK (on by default in smpyests.h) apic_vector.s also contains a small change I (smp) made to eliminate the double level INT problem. It seems stable, but I haven't the tools in place to prove it fixes the problem. Reviewed by: smp@csn.net Submitted by: Tor Egge <Tor.Egge@idi.ntnu.no>
753 lines
18 KiB
ArmAsm
753 lines
18 KiB
ArmAsm
/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $Id: apic_vector.s,v 1.38 1997/12/04 19:46:26 smp Exp smp $
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*/
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#include <machine/apic.h>
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#include <machine/smp.h>
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#include "i386/isa/intr_machdep.h"
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#ifdef FAST_SIMPLELOCK
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#define GET_FAST_INTR_LOCK \
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pushl $_fast_intr_lock ; /* address of lock */ \
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call _s_lock ; /* MP-safe */ \
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addl $4,%esp
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#define REL_FAST_INTR_LOCK \
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pushl $_fast_intr_lock ; /* address of lock */ \
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call _s_unlock ; /* MP-safe */ \
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addl $4,%esp
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#else /* FAST_SIMPLELOCK */
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#define GET_FAST_INTR_LOCK \
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call _get_isrlock
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#define REL_FAST_INTR_LOCK \
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pushl $_mp_lock ; /* GIANT_LOCK */ \
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call _MPrellock ; \
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add $4, %esp
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#endif /* FAST_SIMPLELOCK */
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/* convert an absolute IRQ# into a bitmask */
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#define IRQ_BIT(irq_num) (1 << (irq_num))
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/* make an index into the IO APIC from the IRQ# */
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#define REDTBL_IDX(irq_num) (0x10 + ((irq_num) * 2))
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/*
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* Macros for interrupt interrupt entry, call to handler, and exit.
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*/
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#ifdef FAST_WITHOUTCPL
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/*
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*/
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#define FAST_INTR(irq_num, vec_name) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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pushl %eax ; /* save only call-used registers */ \
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pushl %ecx ; \
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pushl %edx ; \
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pushl %ds ; \
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MAYBE_PUSHL_ES ; \
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movl $KDSEL,%eax ; \
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movl %ax,%ds ; \
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MAYBE_MOVW_AX_ES ; \
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FAKE_MCOUNT((4+ACTUALLY_PUSHED)*4(%esp)) ; \
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pushl _intr_unit + (irq_num) * 4 ; \
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GET_FAST_INTR_LOCK ; \
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call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
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REL_FAST_INTR_LOCK ; \
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addl $4, %esp ; \
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movl $0, lapic_eoi ; \
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lock ; \
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incl _cnt+V_INTR ; /* book-keeping can wait */ \
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movl _intr_countp + (irq_num) * 4, %eax ; \
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lock ; \
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incl (%eax) ; \
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MEXITCOUNT ; \
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MAYBE_POPL_ES ; \
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popl %ds ; \
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popl %edx ; \
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popl %ecx ; \
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popl %eax ; \
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iret
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#else /* FAST_WITHOUTCPL */
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#define FAST_INTR(irq_num, vec_name) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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pushl %eax ; /* save only call-used registers */ \
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pushl %ecx ; \
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pushl %edx ; \
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pushl %ds ; \
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MAYBE_PUSHL_ES ; \
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movl $KDSEL, %eax ; \
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movl %ax, %ds ; \
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MAYBE_MOVW_AX_ES ; \
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FAKE_MCOUNT((4+ACTUALLY_PUSHED)*4(%esp)) ; \
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GET_FAST_INTR_LOCK ; \
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pushl _intr_unit + (irq_num) * 4 ; \
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call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
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addl $4, %esp ; \
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movl $0, lapic_eoi ; \
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lock ; \
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incl _cnt+V_INTR ; /* book-keeping can wait */ \
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movl _intr_countp + (irq_num) * 4,%eax ; \
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lock ; \
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incl (%eax) ; \
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movl _cpl, %eax ; /* unmasking pending HWIs or SWIs? */ \
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notl %eax ; \
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andl _ipending, %eax ; \
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jne 2f ; /* yes, maybe handle them */ \
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1: ; \
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MEXITCOUNT ; \
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REL_FAST_INTR_LOCK ; \
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MAYBE_POPL_ES ; \
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popl %ds ; \
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popl %edx ; \
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popl %ecx ; \
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popl %eax ; \
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iret ; \
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; \
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ALIGN_TEXT ; \
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2: ; \
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cmpb $3, _intr_nesting_level ; /* enough stack? */ \
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jae 1b ; /* no, return */ \
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movl _cpl, %eax ; \
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/* XXX next line is probably unnecessary now. */ \
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movl $HWI_MASK|SWI_MASK, _cpl ; /* limit nesting ... */ \
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lock ; \
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incb _intr_nesting_level ; /* ... really limit it ... */ \
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sti ; /* to do this as early as possible */ \
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MAYBE_POPL_ES ; /* discard most of thin frame ... */ \
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popl %ecx ; /* ... original %ds ... */ \
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popl %edx ; \
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xchgl %eax, 4(%esp) ; /* orig %eax; save cpl */ \
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pushal ; /* build fat frame (grrr) ... */ \
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pushl %ecx ; /* ... actually %ds ... */ \
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pushl %es ; \
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movl $KDSEL, %eax ; \
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movl %ax, %es ; \
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movl (2+8+0)*4(%esp), %ecx ; /* %ecx from thin frame ... */ \
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movl %ecx, (2+6)*4(%esp) ; /* ... to fat frame ... */ \
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movl (2+8+1)*4(%esp), %eax ; /* ... cpl from thin frame */ \
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pushl %eax ; \
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subl $4, %esp ; /* junk for unit number */ \
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MEXITCOUNT ; \
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jmp _doreti
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#endif /** FAST_WITHOUTCPL */
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/*
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*
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*/
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#define PUSH_FRAME \
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pushl $0 ; /* dummy error code */ \
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pushl $0 ; /* dummy trap type */ \
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pushal ; \
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pushl %ds ; /* save data and extra segments ... */ \
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pushl %es
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#define POP_FRAME \
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popl %es ; \
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popl %ds ; \
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popal ; \
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addl $4+4,%esp
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/*
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* Test to see whether we are handling an edge or level triggered INT.
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* Level-triggered INTs must still be masked as we don't clear the source,
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* and the EOI cycle would cause redundant INTs to occur.
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*/
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#define MASK_LEVEL_IRQ(irq_num) \
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testl $IRQ_BIT(irq_num), _apic_pin_trigger ; \
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jz 8f ; /* edge, don't mask */ \
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IMASK_LOCK ; /* into critical reg */ \
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orl $IRQ_BIT(irq_num), _apic_imen ; /* set the mask bit */ \
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movl _ioapic, %ecx ; /* ioapic[0] addr */ \
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movl $REDTBL_IDX(irq_num), (%ecx) ; /* write the index */ \
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movl IOAPIC_WINDOW(%ecx), %eax ; /* current value */ \
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orl $IOART_INTMASK, %eax ; /* set the mask */ \
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movl %eax, IOAPIC_WINDOW(%ecx) ; /* new value */ \
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IMASK_UNLOCK ; \
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8:
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/*
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* Test to see if the source is currntly masked, clear if so.
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*/
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#define UNMASK_IRQ(irq_num) \
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IMASK_LOCK ; /* into critical reg */ \
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testl $IRQ_BIT(irq_num), _apic_imen ; \
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jne 7f ; /* bit set, masked */ \
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testl $IRQ_BIT(irq_num), _apic_pin_trigger ; \
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jz 9f ; /* edge, don't EOI */ \
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movl $0, lapic_eoi ; /* should be safe */ \
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jmp 9f ; /* skip unmasking */ \
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7: \
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andl $~IRQ_BIT(irq_num), _apic_imen ;/* clear mask bit */ \
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movl _ioapic,%ecx ; /* ioapic[0]addr */ \
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movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \
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movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \
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andl $~IOART_INTMASK,%eax ; /* clear the mask */ \
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movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */ \
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9: ; \
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IMASK_UNLOCK
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#ifdef INTR_SIMPLELOCK
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#define ENLOCK
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#define DELOCK
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#define LATELOCK call _get_isrlock
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#else
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#define ENLOCK \
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ISR_TRYLOCK ; /* XXX this is going away... */ \
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testl %eax, %eax ; /* did we get it? */ \
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jz 1f
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#define DELOCK ISR_RELLOCK
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#define LATELOCK
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#endif
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#ifdef CPL_AND_CML
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#define INTR(irq_num, vec_name) \
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.text ; \
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SUPERALIGN_TEXT ; \
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/* _XintrNN: entry point used by IDT/HWIs & splz_unpend via _vec[]. */ \
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IDTVEC(vec_name) ; \
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PUSH_FRAME ; \
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movl $KDSEL, %eax ; /* reload with kernel's data segment */ \
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movl %ax, %ds ; \
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movl %ax, %es ; \
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; \
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lock ; /* MP-safe */ \
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btsl $(irq_num), iactive ; /* lazy masking */ \
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jc 1f ; /* already active */ \
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; \
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ENLOCK ; \
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; \
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AVCPL_LOCK ; /* MP-safe */ \
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testl $IRQ_BIT(irq_num), _cpl ; \
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jne 2f ; /* this INT masked */ \
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testl $IRQ_BIT(irq_num), _cml ; \
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jne 2f ; /* this INT masked */ \
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orl $IRQ_BIT(irq_num), _cil ; \
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AVCPL_UNLOCK ; \
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; \
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;;; movl $0, lapic_eoi ; /* XXX too soon? */ \
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incb _intr_nesting_level ; \
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; \
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/* entry point used by doreti_unpend for HWIs. */ \
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__CONCAT(Xresume,irq_num): ; \
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FAKE_MCOUNT(12*4(%esp)) ; /* XXX avoid dbl cnt */ \
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lock ; incl _cnt+V_INTR ; /* tally interrupts */ \
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movl _intr_countp + (irq_num) * 4, %eax ; \
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lock ; incl (%eax) ; \
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; \
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AVCPL_LOCK ; /* MP-safe */ \
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movl _cml, %eax ; \
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pushl %eax ; \
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orl _intr_mask + (irq_num) * 4, %eax ; \
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movl %eax, _cml ; \
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AVCPL_UNLOCK ; \
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; \
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pushl _intr_unit + (irq_num) * 4 ; \
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incl _inside_intr ; \
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sti ; \
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call *_intr_handler + (irq_num) * 4 ; \
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cli ; \
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decl _inside_intr ; \
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; \
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lock ; andl $~IRQ_BIT(irq_num), iactive ; \
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lock ; andl $~IRQ_BIT(irq_num), _cil ; \
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UNMASK_IRQ(irq_num) ; \
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sti ; /* doreti repeats cli/sti */ \
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MEXITCOUNT ; \
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LATELOCK ; \
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jmp _doreti ; \
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; \
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ALIGN_TEXT ; \
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1: ; /* active or locked */ \
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MASK_LEVEL_IRQ(irq_num) ; \
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movl $0, lapic_eoi ; /* do the EOI */ \
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; \
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AVCPL_LOCK ; /* MP-safe */ \
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orl $IRQ_BIT(irq_num), _ipending ; \
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AVCPL_UNLOCK ; \
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; \
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POP_FRAME ; \
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iret ; \
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; \
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ALIGN_TEXT ; \
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2: ; /* masked by cpl|cml */ \
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AVCPL_UNLOCK ; \
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DELOCK ; /* XXX this is going away... */ \
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jmp 1b
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#else /* CPL_AND_CML */
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#define INTR(irq_num, vec_name) \
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.text ; \
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SUPERALIGN_TEXT ; \
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/* _XintrNN: entry point used by IDT/HWIs & splz_unpend via _vec[]. */ \
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IDTVEC(vec_name) ; \
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PUSH_FRAME ; \
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movl $KDSEL, %eax ; /* reload with kernel's data segment */ \
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movl %ax, %ds ; \
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movl %ax, %es ; \
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; \
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lock ; /* MP-safe */ \
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btsl $(irq_num), iactive ; /* lazy masking */ \
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jc 1f ; /* already active */ \
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; \
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ISR_TRYLOCK ; /* XXX this is going away... */ \
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testl %eax, %eax ; /* did we get it? */ \
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jz 1f ; /* no */ \
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; \
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AVCPL_LOCK ; /* MP-safe */ \
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testl $IRQ_BIT(irq_num), _cpl ; \
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jne 2f ; /* this INT masked */ \
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AVCPL_UNLOCK ; \
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; \
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;;; movl $0, lapic_eoi ; /* XXX too soon? */ \
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incb _intr_nesting_level ; \
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; \
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/* entry point used by doreti_unpend for HWIs. */ \
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__CONCAT(Xresume,irq_num): ; \
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FAKE_MCOUNT(12*4(%esp)) ; /* XXX avoid dbl cnt */ \
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lock ; incl _cnt+V_INTR ; /* tally interrupts */ \
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movl _intr_countp + (irq_num) * 4, %eax ; \
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lock ; incl (%eax) ; \
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; \
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AVCPL_LOCK ; /* MP-safe */ \
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movl _cpl, %eax ; \
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pushl %eax ; \
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orl _intr_mask + (irq_num) * 4, %eax ; \
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movl %eax, _cpl ; \
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AVCPL_UNLOCK ; \
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; \
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pushl _intr_unit + (irq_num) * 4 ; \
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sti ; \
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call *_intr_handler + (irq_num) * 4 ; \
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cli ; \
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; \
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lock ; andl $~IRQ_BIT(irq_num), iactive ; \
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UNMASK_IRQ(irq_num) ; \
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sti ; /* doreti repeats cli/sti */ \
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MEXITCOUNT ; \
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jmp _doreti ; \
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; \
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ALIGN_TEXT ; \
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1: ; /* active or locked */ \
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MASK_LEVEL_IRQ(irq_num) ; \
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movl $0, lapic_eoi ; /* do the EOI */ \
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; \
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AVCPL_LOCK ; /* MP-safe */ \
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orl $IRQ_BIT(irq_num), _ipending ; \
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AVCPL_UNLOCK ; \
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; \
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POP_FRAME ; \
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iret ; \
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; \
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ALIGN_TEXT ; \
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2: ; /* masked by cpl */ \
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AVCPL_UNLOCK ; \
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ISR_RELLOCK ; /* XXX this is going away... */ \
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jmp 1b
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#endif /* CPL_AND_CML */
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/*
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* Handle "spurious INTerrupts".
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* Notes:
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* This is different than the "spurious INTerrupt" generated by an
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* 8259 PIC for missing INTs. See the APIC documentation for details.
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* This routine should NOT do an 'EOI' cycle.
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*/
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.text
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SUPERALIGN_TEXT
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.globl _Xspuriousint
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_Xspuriousint:
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/* No EOI cycle used here */
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iret
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/*
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* Handle TLB shootdowns.
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*/
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.text
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SUPERALIGN_TEXT
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.globl _Xinvltlb
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_Xinvltlb:
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pushl %eax
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#ifdef COUNT_XINVLTLB_HITS
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ss
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movl _cpuid, %eax
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ss
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incl _xhits(,%eax,4)
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#endif /* COUNT_XINVLTLB_HITS */
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movl %cr3, %eax /* invalidate the TLB */
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movl %eax, %cr3
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ss /* stack segment, avoid %ds load */
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movl $0, lapic_eoi /* End Of Interrupt to APIC */
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popl %eax
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iret
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#ifdef BETTER_CLOCK
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/*
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* Executed by a CPU when it receives an Xcpucheckstate IPI from another CPU,
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*
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* - Stores current cpu state in checkstate_cpustate[cpuid]
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* 0 == user, 1 == sys, 2 == intr
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* - Stores current process in checkstate_curproc[cpuid]
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*
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* - Signals its receipt by setting bit cpuid in checkstate_probed_cpus.
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*
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* stack: 0 -> ds, 4 -> ebx, 8 -> eax, 12 -> eip, 16 -> cs, 20 -> eflags
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*/
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.text
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SUPERALIGN_TEXT
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.globl _Xcpucheckstate
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.globl _checkstate_cpustate
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.globl _checkstate_curproc
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.globl _checkstate_pc
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_Xcpucheckstate:
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pushl %eax
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pushl %ebx
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pushl %ds /* save current data segment */
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movl $KDSEL, %eax
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movl %ax, %ds /* use KERNEL data segment */
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movl $0, lapic_eoi /* End Of Interrupt to APIC */
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movl $0, %ebx
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movl 16(%esp), %eax
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andl $3, %eax
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cmpl $3, %eax
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je 1f
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#ifdef VM86
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testl $PSL_VM, 20(%esp)
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jne 1f
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#endif
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incl %ebx /* system or interrupt */
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#ifdef CPL_AND_CML
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cmpl $0, _inside_intr
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je 1f
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incl %ebx /* interrupt */
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#endif
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1:
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movl _cpuid, %eax
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movl %ebx, _checkstate_cpustate(,%eax,4)
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movl _curproc, %ebx
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movl %ebx, _checkstate_curproc(,%eax,4)
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movl 12(%esp), %ebx
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movl %ebx, _checkstate_pc(,%eax,4)
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lock /* checkstate_probed_cpus |= (1<<id) */
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btsl %eax, _checkstate_probed_cpus
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popl %ds /* restore previous data segment */
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popl %ebx
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popl %eax
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iret
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/*
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* Executed by a CPU when it receives an Xcpuast IPI from another CPU,
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*
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* - Signals its receipt by clearing bit cpuid in checkstate_need_ast.
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*
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* - We need a better method of triggering asts on other cpus.
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*/
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.text
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SUPERALIGN_TEXT
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.globl _Xcpuast
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|
_Xcpuast:
|
|
PUSH_FRAME
|
|
movl $KDSEL, %eax
|
|
movl %ax, %ds /* use KERNEL data segment */
|
|
movl %ax, %es
|
|
|
|
movl _cpuid, %eax
|
|
lock /* checkstate_need_ast &= ~(1<<id) */
|
|
btrl %eax, _checkstate_need_ast
|
|
movl $0, lapic_eoi /* End Of Interrupt to APIC */
|
|
|
|
lock
|
|
btsl %eax, _checkstate_pending_ast
|
|
jc 1f
|
|
|
|
FAKE_MCOUNT(12*4(%esp))
|
|
|
|
/*
|
|
* Giant locks do not come cheap.
|
|
* A lot of cycles are going to be wasted here.
|
|
*/
|
|
call _get_isrlock
|
|
|
|
AVCPL_LOCK
|
|
#ifdef CPL_AND_CML
|
|
movl _cml, %eax
|
|
#else
|
|
movl _cpl, %eax
|
|
#endif
|
|
pushl %eax
|
|
AVCPL_UNLOCK
|
|
lock
|
|
incb _intr_nesting_level
|
|
sti
|
|
|
|
pushl $0
|
|
|
|
lock
|
|
orl $SWI_AST_PENDING, _ipending
|
|
|
|
movl _cpuid, %eax
|
|
lock
|
|
btrl %eax, _checkstate_pending_ast
|
|
|
|
MEXITCOUNT
|
|
jmp _doreti
|
|
1:
|
|
/* We are already in the process of delivering an ast for this CPU */
|
|
POP_FRAME
|
|
iret
|
|
|
|
#endif /* BETTER_CLOCK */
|
|
|
|
|
|
/*
|
|
* Executed by a CPU when it receives an Xcpustop IPI from another CPU,
|
|
*
|
|
* - Signals its receipt.
|
|
* - Waits for permission to restart.
|
|
* - Signals its restart.
|
|
*/
|
|
|
|
.text
|
|
SUPERALIGN_TEXT
|
|
.globl _Xcpustop
|
|
_Xcpustop:
|
|
pushl %eax
|
|
pushl %ds /* save current data segment */
|
|
|
|
movl $KDSEL, %eax
|
|
movl %ax, %ds /* use KERNEL data segment */
|
|
|
|
movl _cpuid, %eax
|
|
|
|
lock
|
|
btsl %eax, _stopped_cpus /* stopped_cpus |= (1<<id) */
|
|
1:
|
|
btl %eax, _started_cpus /* while (!(started_cpus & (1<<id))) */
|
|
jnc 1b
|
|
|
|
lock
|
|
btrl %eax, _started_cpus /* started_cpus &= ~(1<<id) */
|
|
|
|
movl $0, lapic_eoi /* End Of Interrupt to APIC */
|
|
|
|
popl %ds /* restore previous data segment */
|
|
popl %eax
|
|
iret
|
|
|
|
|
|
MCOUNT_LABEL(bintr)
|
|
FAST_INTR(0,fastintr0)
|
|
FAST_INTR(1,fastintr1)
|
|
FAST_INTR(2,fastintr2)
|
|
FAST_INTR(3,fastintr3)
|
|
FAST_INTR(4,fastintr4)
|
|
FAST_INTR(5,fastintr5)
|
|
FAST_INTR(6,fastintr6)
|
|
FAST_INTR(7,fastintr7)
|
|
FAST_INTR(8,fastintr8)
|
|
FAST_INTR(9,fastintr9)
|
|
FAST_INTR(10,fastintr10)
|
|
FAST_INTR(11,fastintr11)
|
|
FAST_INTR(12,fastintr12)
|
|
FAST_INTR(13,fastintr13)
|
|
FAST_INTR(14,fastintr14)
|
|
FAST_INTR(15,fastintr15)
|
|
FAST_INTR(16,fastintr16)
|
|
FAST_INTR(17,fastintr17)
|
|
FAST_INTR(18,fastintr18)
|
|
FAST_INTR(19,fastintr19)
|
|
FAST_INTR(20,fastintr20)
|
|
FAST_INTR(21,fastintr21)
|
|
FAST_INTR(22,fastintr22)
|
|
FAST_INTR(23,fastintr23)
|
|
INTR(0,intr0)
|
|
INTR(1,intr1)
|
|
INTR(2,intr2)
|
|
INTR(3,intr3)
|
|
INTR(4,intr4)
|
|
INTR(5,intr5)
|
|
INTR(6,intr6)
|
|
INTR(7,intr7)
|
|
INTR(8,intr8)
|
|
INTR(9,intr9)
|
|
INTR(10,intr10)
|
|
INTR(11,intr11)
|
|
INTR(12,intr12)
|
|
INTR(13,intr13)
|
|
INTR(14,intr14)
|
|
INTR(15,intr15)
|
|
INTR(16,intr16)
|
|
INTR(17,intr17)
|
|
INTR(18,intr18)
|
|
INTR(19,intr19)
|
|
INTR(20,intr20)
|
|
INTR(21,intr21)
|
|
INTR(22,intr22)
|
|
INTR(23,intr23)
|
|
MCOUNT_LABEL(eintr)
|
|
|
|
.data
|
|
/*
|
|
* Addresses of interrupt handlers.
|
|
* XresumeNN: Resumption addresses for HWIs.
|
|
*/
|
|
.globl _ihandlers
|
|
_ihandlers:
|
|
ihandlers:
|
|
/*
|
|
* used by:
|
|
* ipl.s: doreti_unpend
|
|
*/
|
|
.long Xresume0, Xresume1, Xresume2, Xresume3
|
|
.long Xresume4, Xresume5, Xresume6, Xresume7
|
|
.long Xresume8, Xresume9, Xresume10, Xresume11
|
|
.long Xresume12, Xresume13, Xresume14, Xresume15
|
|
.long Xresume16, Xresume17, Xresume18, Xresume19
|
|
.long Xresume20, Xresume21, Xresume22, Xresume23
|
|
/*
|
|
* used by:
|
|
* ipl.s: doreti_unpend
|
|
* apic_ipl.s: splz_unpend
|
|
*/
|
|
.long swi_tty, swi_net
|
|
.long dummycamisr, dummycamisr
|
|
.long 0, 0
|
|
.long _softclock, swi_ast
|
|
|
|
imasks: /* masks for interrupt handlers */
|
|
.space NHWI*4 /* padding; HWI masks are elsewhere */
|
|
|
|
.long SWI_TTY_MASK, SWI_NET_MASK
|
|
.long SWI_CAMNET_MASK, SWI_CAMBIO_MASK
|
|
.long 0, 0
|
|
.long SWI_CLOCK_MASK, SWI_AST_MASK
|
|
|
|
/*
|
|
* IDT vector entry points for the HWIs.
|
|
*
|
|
* used by:
|
|
* i386/isa/clock.c: setup Xintr8254
|
|
*/
|
|
.globl _ivectors
|
|
_ivectors:
|
|
.long _Xintr0, _Xintr1, _Xintr2, _Xintr3
|
|
.long _Xintr4, _Xintr5, _Xintr6, _Xintr7
|
|
.long _Xintr8, _Xintr9, _Xintr10, _Xintr11
|
|
.long _Xintr12, _Xintr13, _Xintr14, _Xintr15
|
|
.long _Xintr16, _Xintr17, _Xintr18, _Xintr19
|
|
.long _Xintr20, _Xintr21, _Xintr22, _Xintr23
|
|
|
|
/* active flag for lazy masking */
|
|
iactive:
|
|
.long 0
|
|
|
|
#ifdef COUNT_XINVLTLB_HITS
|
|
.globl _xhits
|
|
_xhits:
|
|
.space (NCPU * 4), 0
|
|
#endif /* COUNT_XINVLTLB_HITS */
|
|
|
|
/* variables used by stop_cpus()/restart_cpus()/Xcpustop */
|
|
.globl _stopped_cpus, _started_cpus
|
|
_stopped_cpus:
|
|
.long 0
|
|
_started_cpus:
|
|
.long 0
|
|
|
|
#ifdef BETTER_CLOCK
|
|
.globl _checkstate_probed_cpus
|
|
.globl _checkstate_need_ast
|
|
_checkstate_probed_cpus:
|
|
.long 0
|
|
_checkstate_need_ast:
|
|
.long 0
|
|
_checkstate_pending_ast:
|
|
.long 0
|
|
#endif
|
|
|
|
.globl _apic_pin_trigger
|
|
_apic_pin_trigger:
|
|
.space (NAPIC * 4), 0
|
|
|
|
|
|
/*
|
|
* Interrupt counters and names. The format of these and the label names
|
|
* must agree with what vmstat expects. The tables are indexed by device
|
|
* ids so that we don't have to move the names around as devices are
|
|
* attached.
|
|
*/
|
|
#include "vector.h"
|
|
.globl _intrcnt, _eintrcnt
|
|
_intrcnt:
|
|
.space (NR_DEVICES + ICU_LEN) * 4
|
|
_eintrcnt:
|
|
|
|
.globl _intrnames, _eintrnames
|
|
_intrnames:
|
|
.ascii DEVICE_NAMES
|
|
.asciz "stray irq0"
|
|
.asciz "stray irq1"
|
|
.asciz "stray irq2"
|
|
.asciz "stray irq3"
|
|
.asciz "stray irq4"
|
|
.asciz "stray irq5"
|
|
.asciz "stray irq6"
|
|
.asciz "stray irq7"
|
|
.asciz "stray irq8"
|
|
.asciz "stray irq9"
|
|
.asciz "stray irq10"
|
|
.asciz "stray irq11"
|
|
.asciz "stray irq12"
|
|
.asciz "stray irq13"
|
|
.asciz "stray irq14"
|
|
.asciz "stray irq15"
|
|
.asciz "stray irq16"
|
|
.asciz "stray irq17"
|
|
.asciz "stray irq18"
|
|
.asciz "stray irq19"
|
|
.asciz "stray irq20"
|
|
.asciz "stray irq21"
|
|
.asciz "stray irq22"
|
|
.asciz "stray irq23"
|
|
_eintrnames:
|
|
|
|
.text
|