73efa2fbd1
- Remove the arm64-specific cpu_*cache* and cpu_tlb_flush* functions. Instead, add RISC-V specific inline functions in cpufunc.h for the fence.i and sfence.vma instructions. - Catch up to changes in the arm64 pmap and remove all the cpu_dcache_* calls, pmap_is_current, pmap_l3_valid_cacheable, and PTE_NEXT bits from pmap. - Remove references to the unimplemented riscv_setttb(). - Remove unused cpu_nullop. - Add a link to the SBI doc to sbi.h. - Add support for a 4th argument in SBI calls. It's not documented but it seems implied for the asid argument to SBI_REMOVE_SFENCE_VMA_ASID. - Pass the arguments from sbi_remote_sfence*() to the SEE. BBL ignores them so this is just cosmetic. - Flush icaches on other CPUs when they resume from kdb in case the debugger wrote any breakpoints while the CPUs were paused in the IPI_STOP handler. - Add SMP vs UP versions of pmap_invalidate_* similar to amd64. The UP versions just use simple fences. The SMP versions use the sbi_remove_sfence*() functions to perform TLB shootdowns. Since we don't have a valid pm_active field in the riscv pmap, just IPI all CPUs for all invalidations for now. - Remove an extraneous TLB flush from the end of pmap_bootstrap(). - Don't do a TLB flush when writing new mappings in pmap_enter(), only if modifying an existing mapping. Note that for COW faults a TLB flush is only performed after explicitly clearing the old mapping as is done in other pmaps. - Sync the i-cache on all harts before updating the PTE for executable mappings in pmap_enter and pmap_enter_quick. Previously the i-cache was only sync'd after updating the PTE in pmap_enter. - Use sbi_remote_fence() instead of smp_rendezvous in pmap_sync_icache(). Reviewed by: markj Approved by: re (gjb, kib) Sponsored by: DARPA Differential Revision: https://reviews.freebsd.org/D17414
142 lines
3.9 KiB
C
142 lines
3.9 KiB
C
/*-
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* Copyright (c) 2016-2017 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_SBI_H_
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#define _MACHINE_SBI_H_
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#define SBI_SET_TIMER 0
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#define SBI_CONSOLE_PUTCHAR 1
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#define SBI_CONSOLE_GETCHAR 2
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#define SBI_CLEAR_IPI 3
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#define SBI_SEND_IPI 4
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#define SBI_REMOTE_FENCE_I 5
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#define SBI_REMOTE_SFENCE_VMA 6
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#define SBI_REMOTE_SFENCE_VMA_ASID 7
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#define SBI_SHUTDOWN 8
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/*
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* Documentation available at
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* https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md
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*/
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static __inline uint64_t
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sbi_call(uint64_t arg7, uint64_t arg0, uint64_t arg1, uint64_t arg2,
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uint64_t arg3)
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{
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register uintptr_t a0 __asm ("a0") = (uintptr_t)(arg0);
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register uintptr_t a1 __asm ("a1") = (uintptr_t)(arg1);
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register uintptr_t a2 __asm ("a2") = (uintptr_t)(arg2);
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register uintptr_t a3 __asm ("a3") = (uintptr_t)(arg3);
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register uintptr_t a7 __asm ("a7") = (uintptr_t)(arg7);
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__asm __volatile( \
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"ecall" \
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:"+r"(a0) \
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:"r"(a1), "r"(a2), "r" (a3), "r"(a7) \
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:"memory");
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return (a0);
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}
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static __inline void
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sbi_console_putchar(int ch)
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{
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sbi_call(SBI_CONSOLE_PUTCHAR, ch, 0, 0, 0);
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}
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static __inline int
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sbi_console_getchar(void)
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{
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return (sbi_call(SBI_CONSOLE_GETCHAR, 0, 0, 0, 0));
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}
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static __inline void
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sbi_set_timer(uint64_t val)
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{
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sbi_call(SBI_SET_TIMER, val, 0, 0, 0);
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}
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static __inline void
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sbi_shutdown(void)
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{
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sbi_call(SBI_SHUTDOWN, 0, 0, 0, 0);
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}
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static __inline void
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sbi_clear_ipi(void)
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{
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sbi_call(SBI_CLEAR_IPI, 0, 0, 0, 0);
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}
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static __inline void
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sbi_send_ipi(const unsigned long *hart_mask)
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{
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sbi_call(SBI_SEND_IPI, (uint64_t)hart_mask, 0, 0, 0);
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}
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static __inline void
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sbi_remote_fence_i(const unsigned long *hart_mask)
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{
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sbi_call(SBI_REMOTE_FENCE_I, (uint64_t)hart_mask, 0, 0, 0);
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}
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static __inline void
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sbi_remote_sfence_vma(const unsigned long *hart_mask,
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unsigned long start, unsigned long size)
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{
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sbi_call(SBI_REMOTE_SFENCE_VMA, (uint64_t)hart_mask, start, size, 0);
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}
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static __inline void
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sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
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unsigned long start, unsigned long size,
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unsigned long asid)
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{
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sbi_call(SBI_REMOTE_SFENCE_VMA_ASID, (uint64_t)hart_mask, start, size,
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asid);
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}
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#endif /* !_MACHINE_SBI_H_ */
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