54a8c69347
Interrupts under the new scheme are managed by the i386 nexus with the awareness of the resource manager. There is further room for optimizing the interfaces still. All the users of register_intr()/intr_create() should be gone, with the exception of pcic and i386/isa/clock.c.
418 lines
10 KiB
C
418 lines
10 KiB
C
/*-
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* Copyright (c) 1997 Bruce Evans.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: ipl_funcs.c,v 1.15 1999/03/05 23:39:02 gibbs Exp $
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*/
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <machine/ipl.h>
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#ifndef SMP
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/*
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* The volatile bitmap variables must be set atomically. This normally
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* involves using a machine-dependent bit-set or `or' instruction.
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*/
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#define DO_SETBITS(name, var, bits) \
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void name(void) \
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{ \
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setbits(var, bits); \
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}
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DO_SETBITS(setdelayed, &ipending, loadandclear((unsigned *)&idelayed))
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DO_SETBITS(setsoftast, &ipending, SWI_AST_PENDING)
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DO_SETBITS(setsoftcamnet,&ipending, SWI_CAMNET_PENDING)
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DO_SETBITS(setsoftcambio,&ipending, SWI_CAMBIO_PENDING)
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DO_SETBITS(setsoftclock, &ipending, SWI_CLOCK_PENDING)
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DO_SETBITS(setsoftnet, &ipending, SWI_NET_PENDING)
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DO_SETBITS(setsofttty, &ipending, SWI_TTY_PENDING)
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DO_SETBITS(setsoftvm, &ipending, SWI_VM_PENDING)
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DO_SETBITS(schedsoftcamnet, &idelayed, SWI_CAMNET_PENDING)
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DO_SETBITS(schedsoftcambio, &idelayed, SWI_CAMBIO_PENDING)
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DO_SETBITS(schedsoftnet, &idelayed, SWI_NET_PENDING)
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DO_SETBITS(schedsofttty, &idelayed, SWI_TTY_PENDING)
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DO_SETBITS(schedsoftvm, &idelayed, SWI_VM_PENDING)
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unsigned
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softclockpending(void)
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{
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return (ipending & SWI_CLOCK_PENDING);
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}
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#define GENSPL(name, set_cpl) \
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unsigned name(void) \
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{ \
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unsigned x; \
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\
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x = cpl; \
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set_cpl; \
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return (x); \
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}
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GENSPL(splbio, cpl |= bio_imask)
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GENSPL(splcam, cpl |= cam_imask)
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GENSPL(splclock, cpl = HWI_MASK | SWI_MASK)
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GENSPL(splhigh, cpl = HWI_MASK | SWI_MASK)
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GENSPL(splimp, cpl |= net_imask)
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GENSPL(splnet, cpl |= SWI_NET_MASK)
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GENSPL(splsoftcam, cpl |= SWI_CAMBIO_MASK | SWI_CAMNET_MASK)
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GENSPL(splsoftcambio, cpl |= SWI_CAMBIO_MASK)
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GENSPL(splsoftcamnet, cpl |= SWI_CAMNET_MASK)
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GENSPL(splsoftclock, cpl = SWI_CLOCK_MASK)
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GENSPL(splsofttty, cpl |= SWI_TTY_MASK)
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GENSPL(splsoftvm, cpl |= SWI_VM_MASK)
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GENSPL(splstatclock, cpl |= stat_imask)
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GENSPL(spltty, cpl |= tty_imask)
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GENSPL(splvm, cpl |= net_imask | bio_imask | cam_imask)
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void
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spl0(void)
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{
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cpl = SWI_AST_MASK;
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if (ipending & ~SWI_AST_MASK)
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splz();
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}
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void
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splx(unsigned ipl)
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{
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cpl = ipl;
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if (ipending & ~ipl)
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splz();
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}
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intrmask_t
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splq(intrmask_t mask)
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{
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intrmask_t tmp = cpl;
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cpl |= mask;
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return (tmp);
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}
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#else /* !SMP */
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#include <machine/smp.h>
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#include <machine/smptests.h>
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#ifndef SPL_DEBUG_POSTCODE
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#undef POSTCODE
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#undef POSTCODE_LO
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#undef POSTCODE_HI
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#define POSTCODE(X)
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#define POSTCODE_LO(X)
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#define POSTCODE_HI(X)
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#endif /* SPL_DEBUG_POSTCODE */
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/*
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* The volatile bitmap variables must be set atomically. This normally
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* involves using a machine-dependent bit-set or `or' instruction.
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*/
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#define DO_SETBITS(name, var, bits) \
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void name(void) \
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{ \
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IFCPL_LOCK(); \
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setbits(var, bits); \
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IFCPL_UNLOCK(); \
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}
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DO_SETBITS(setdelayed, &ipending, loadandclear((unsigned *)&idelayed))
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DO_SETBITS(setsoftast, &ipending, SWI_AST_PENDING)
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DO_SETBITS(setsoftcamnet,&ipending, SWI_CAMNET_PENDING)
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DO_SETBITS(setsoftcambio,&ipending, SWI_CAMBIO_PENDING)
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DO_SETBITS(setsoftclock, &ipending, SWI_CLOCK_PENDING)
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DO_SETBITS(setsoftnet, &ipending, SWI_NET_PENDING)
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DO_SETBITS(setsofttty, &ipending, SWI_TTY_PENDING)
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DO_SETBITS(setsoftvm, &ipending, SWI_VM_PENDING)
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DO_SETBITS(schedsoftcamnet, &idelayed, SWI_CAMNET_PENDING)
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DO_SETBITS(schedsoftcambio, &idelayed, SWI_CAMBIO_PENDING)
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DO_SETBITS(schedsoftnet, &idelayed, SWI_NET_PENDING)
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DO_SETBITS(schedsofttty, &idelayed, SWI_TTY_PENDING)
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DO_SETBITS(schedsoftvm, &idelayed, SWI_VM_PENDING)
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unsigned
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softclockpending(void)
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{
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unsigned x;
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IFCPL_LOCK();
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x = ipending & SWI_CLOCK_PENDING;
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IFCPL_UNLOCK();
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return (x);
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}
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/*
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* This version has to check for bsp_apic_ready,
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* as calling simple_lock() (ie ss_lock) before then deadlocks the system.
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* A sample count of GENSPL calls before bsp_apic_ready was set: 2193
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*/
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#ifdef INTR_SPL
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#ifdef SPL_DEBUG
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#define MAXZ 100000000
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#define SPIN_VAR unsigned z;
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#define SPIN_RESET z = 0;
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#if 0
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#define SPIN_SPL \
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if (++z >= MAXZ) { \
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/* XXX allow lock-free panic */ \
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bsp_apic_ready = 0; \
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panic("\ncil: 0x%08x", cil); \
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}
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#else
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#define SPIN_SPL \
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if (++z >= MAXZ) { \
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/* XXX allow lock-free panic */ \
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bsp_apic_ready = 0; \
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printf("\ncil: 0x%08x", cil); \
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breakpoint(); \
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}
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#endif /* 0/1 */
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#else /* SPL_DEBUG */
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#define SPIN_VAR
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#define SPIN_RESET
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#define SPIN_SPL
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#endif /* SPL_DEBUG */
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#endif
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#ifdef INTR_SPL
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#define GENSPL(NAME, OP, MODIFIER, PC) \
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unsigned NAME(void) \
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{ \
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unsigned x, y; \
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SPIN_VAR; \
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\
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if (!bsp_apic_ready) { \
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x = cpl; \
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cpl OP MODIFIER; \
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return (x); \
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} \
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\
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for (;;) { \
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IFCPL_LOCK(); /* MP-safe */ \
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x = y = cpl; /* current value */ \
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POSTCODE(0x20 | PC); \
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if (inside_intr) \
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break; /* XXX only 1 INT allowed */ \
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y OP MODIFIER; /* desired value */ \
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if (cil & y) { /* not now */ \
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IFCPL_UNLOCK(); /* allow cil to change */ \
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SPIN_RESET; \
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while (cil & y) \
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SPIN_SPL \
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continue; /* try again */ \
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} \
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break; \
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} \
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cpl OP MODIFIER; /* make the change */ \
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IFCPL_UNLOCK(); \
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\
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return (x); \
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}
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/* NAME: OP: MODIFIER: PC: */
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GENSPL(splbio, |=, bio_imask, 2)
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GENSPL(splcam, |=, cam_imask, 7)
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GENSPL(splclock, =, HWI_MASK | SWI_MASK, 3)
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GENSPL(splhigh, =, HWI_MASK | SWI_MASK, 4)
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GENSPL(splimp, |=, net_imask, 5)
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GENSPL(splnet, |=, SWI_NET_MASK, 6)
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GENSPL(splsoftcam, |=, SWI_CAMBIO_MASK | SWI_CAMNET_MASK, 8)
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GENSPL(splsoftcambio, |=, SWI_CAMBIO_MASK, 9)
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GENSPL(splsoftcamnet, |=, SWI_CAMNET_MASK, 10)
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GENSPL(splsoftclock, =, SWI_CLOCK_MASK, 11)
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GENSPL(splsofttty, |=, SWI_TTY_MASK, 12)
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GENSPL(splsoftvm, |=, SWI_VM_MASK, 16)
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GENSPL(splstatclock, |=, stat_imask, 13)
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GENSPL(spltty, |=, tty_imask, 14)
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GENSPL(splvm, |=, net_imask | bio_imask | cam_imask, 15)
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#else /* INTR_SPL */
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#define GENSPL(NAME, set_cpl) \
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unsigned NAME(void) \
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{ \
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unsigned x; \
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\
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if (!bsp_apic_ready) { \
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x = cpl; \
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set_cpl; \
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} \
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else { \
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IFCPL_LOCK(); \
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x = cpl; \
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set_cpl; \
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IFCPL_UNLOCK(); \
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} \
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\
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return (x); \
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}
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GENSPL(splbio, cpl |= bio_imask)
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GENSPL(splclock, cpl = HWI_MASK | SWI_MASK)
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GENSPL(splhigh, cpl = HWI_MASK | SWI_MASK)
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GENSPL(splimp, cpl |= net_imask)
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GENSPL(splnet, cpl |= SWI_NET_MASK)
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GENSPL(splcam, cpl |= cam_imask)
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GENSPL(splsoftcam, cpl |= SWI_CAMBIO_MASK | SWI_CAMNET_MASK)
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GENSPL(splsoftcambio, cpl |= SWI_CAMBIO_MASK)
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GENSPL(splsoftcamnet, cpl |= SWI_CAMNET_MASK)
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GENSPL(splsoftclock, cpl = SWI_CLOCK_MASK)
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GENSPL(splsofttty, cpl |= SWI_TTY_MASK)
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GENSPL(splsoftvm, cpl |= SWI_VM_MASK)
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GENSPL(splstatclock, cpl |= stat_imask)
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GENSPL(spltty, cpl |= tty_imask)
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GENSPL(splvm, cpl |= net_imask | bio_imask | cam_imask)
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#endif /* INTR_SPL */
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void
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spl0(void)
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{
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int unpend;
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#ifdef INTR_SPL
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SPIN_VAR;
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for (;;) {
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IFCPL_LOCK();
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POSTCODE_HI(0xc);
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if (cil & SWI_AST_MASK) { /* not now */
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IFCPL_UNLOCK(); /* allow cil to change */
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SPIN_RESET;
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while (cil & SWI_AST_MASK)
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SPIN_SPL
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continue; /* try again */
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}
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break;
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}
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#else /* INTR_SPL */
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IFCPL_LOCK();
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#endif /* INTR_SPL */
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cpl = SWI_AST_MASK;
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unpend = ipending & ~SWI_AST_MASK;
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IFCPL_UNLOCK();
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if (unpend && !inside_intr)
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splz();
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}
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void
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splx(unsigned ipl)
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{
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int unpend;
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#ifdef INTR_SPL
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SPIN_VAR;
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#endif
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if (!bsp_apic_ready) {
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cpl = ipl;
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if (ipending & ~ipl)
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splz();
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return;
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}
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#ifdef INTR_SPL
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for (;;) {
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IFCPL_LOCK();
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POSTCODE_HI(0xe);
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if (inside_intr)
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break; /* XXX only 1 INT allowed */
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POSTCODE_HI(0xf);
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if (cil & ipl) { /* not now */
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IFCPL_UNLOCK(); /* allow cil to change */
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SPIN_RESET;
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while (cil & ipl)
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SPIN_SPL
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continue; /* try again */
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}
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break;
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}
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#else /* INTR_SPL */
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IFCPL_LOCK();
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#endif /* INTR_SPL */
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cpl = ipl;
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unpend = ipending & ~ipl;
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IFCPL_UNLOCK();
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if (unpend && !inside_intr)
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splz();
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}
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/*
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* Replaces UP specific inline found in (?) pci/pci_support.c.
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*
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* Stefan said:
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* You know, that splq() is used in the shared interrupt multiplexer, and that
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* the SMP version should not have too much overhead. If it is significantly
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* slower, then moving the splq() out of the loop in intr_mux() and passing in
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* the logical OR of all mask values might be a better solution than the
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* current code. (This logical OR could of course be pre-calculated whenever
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* another shared interrupt is registered ...)
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*/
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intrmask_t
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splq(intrmask_t mask)
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{
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intrmask_t tmp;
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#ifdef INTR_SPL
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intrmask_t tmp2;
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for (;;) {
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IFCPL_LOCK();
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tmp = tmp2 = cpl;
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tmp2 |= mask;
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if (cil & tmp2) { /* not now */
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IFCPL_UNLOCK(); /* allow cil to change */
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while (cil & tmp2)
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/* spin */ ;
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continue; /* try again */
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}
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break;
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}
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cpl = tmp2;
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#else /* INTR_SPL */
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IFCPL_LOCK();
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tmp = cpl;
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cpl |= mask;
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#endif /* INTR_SPL */
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IFCPL_UNLOCK();
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return (tmp);
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}
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#endif /* !SMP */
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