54dd351d93
If we can, use timeouts instead of DELAYs when dealing with a bus reset. This prevents us from holding up the whole machine for a noticible amount of time (especially for a real time app). Make a pass over the timeout/error handling code. Aborts are more reliable. We actually handle parity errors correctly now instead of locking up the bus. Added code to properly clean up disconnected SCBs down on the card during error handling. Improved robustness in several areas. If we are using defaults, but are an Ultra card, negotiate at 20MHz instead of 10. Don't attempt to handle any commands for 100ms after a reset has occured. This is the minimum time before a target will respond to selection. Also disable the busfree interrupt before doing a bus reset. This prevents the driver from getting confused by an "unexpected busfree".
385 lines
11 KiB
C
385 lines
11 KiB
C
/*
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* Interface to the generic driver for the aic7xxx based adaptec
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* SCSI controllers. This is used to implement product specific
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* probe and attach routines.
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*
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* Copyright (c) 1994, 1995, 1996, 1997 Justin T. Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _AIC7XXX_H_
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#define _AIC7XXX_H_
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#if defined(__FreeBSD__)
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#include "ahc.h" /* for NAHC from config */
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#include "opt_aic7xxx.h" /* for config options */
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#endif
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#if defined(__NetBSD__)
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/*
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* convert FreeBSD's <sys/queue.h> symbols to NetBSD's
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*/
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#define STAILQ_ENTRY SIMPLEQ_ENTRY
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#define STAILQ_HEAD SIMPLEQ_HEAD
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#define STAILQ_INIT SIMPLEQ_INIT
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#define STAILQ_INSERT_HEAD SIMPLEQ_INSERT_HEAD
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#define STAILQ_INSERT_TAIL SIMPLEQ_INSERT_TAIL
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#define STAILQ_REMOVE_HEAD(head, field) \
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SIMPLEQ_REMOVE_HEAD(head, (head)->sqh_first, field)
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#define stqh_first sqh_first
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#define stqe_next sqe_next
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#endif
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#define AHC_NSEG 256 /* number of dma segments supported */
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#define AHC_SCB_MAX 255 /*
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* Up to 255 SCBs on some types of aic7xxx
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* based boards. The aic7870 have 16 internal
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* SCBs, but external SRAM bumps this to 255.
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* The aic7770 family have only 4, and the
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* aic7850 has only 3.
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*/
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typedef u_int32_t physaddr;
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#if defined(__FreeBSD__)
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extern u_long ahc_unit;
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#endif
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struct ahc_dma_seg {
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physaddr addr;
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u_int32_t len;
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};
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typedef enum {
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AHC_NONE = 0x0000,
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AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */
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AHC_WIDE = 0x0002, /* Wide Channel */
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AHC_TWIN = 0x0008, /* Twin Channel */
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AHC_AIC7770 = 0x0010,
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AHC_AIC7850 = 0x0020,
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AHC_AIC7860 = 0x0021, /* ULTRA version of the aic7850 */
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AHC_AIC7870 = 0x0040,
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AHC_AIC7880 = 0x0041,
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AHC_AIC78X0 = 0x0060, /* PCI Based Controller */
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AHC_274 = 0x0110, /* EISA Based Controller */
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AHC_284 = 0x0210, /* VL/ISA Based Controller */
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AHC_294AU = 0x0421, /* aic7860 based '2940' */
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AHC_294 = 0x0440, /* PCI Based Controller */
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AHC_294U = 0x0441, /* ULTRA PCI Based Controller */
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AHC_394 = 0x0840, /* Twin Channel PCI Controller */
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AHC_394U = 0x0841, /* ULTRA, Twin Channel PCI Controller */
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AHC_398 = 0x1040, /* Multi Channel PCI RAID Controller */
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AHC_398U = 0x1041, /* ULTRA, Multi Channel PCI
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* RAID Controller
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*/
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AHC_39X = 0x1800 /* Multi Channel PCI Adapter */
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}ahc_type;
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typedef enum {
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AHC_FNONE = 0x00,
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AHC_INIT = 0x01,
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AHC_RUNNING = 0x02,
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AHC_PAGESCBS = 0x04, /* Enable SCB paging */
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AHC_CHANNEL_B_PRIMARY = 0x08, /*
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* On twin channel adapters, probe
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* channel B first since it is the
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* primary bus.
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*/
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AHC_USEDEFAULTS = 0x10, /*
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* For cards without an seeprom
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* or a BIOS to initialize the chip's
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* SRAM, we use the default target
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* settings.
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*/
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AHC_CHNLB = 0x20, /*
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* Second controller on 3940/398X
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* Also encodes the offset in the
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* SEEPROM for CHNLB info (32)
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*/
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AHC_CHNLC = 0x40 /*
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* Third controller on 3985
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* Also encodes the offset in the
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* SEEPROM for CHNLC info (64)
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*/
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} ahc_flag;
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typedef enum {
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SCB_FREE = 0x0000,
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SCB_ACTIVE = 0x0001,
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SCB_ABORTED = 0x0002,
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SCB_DEVICE_RESET = 0x0004,
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SCB_IMMED = 0x0008,
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SCB_SENSE = 0x0010,
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SCB_TIMEDOUT = 0x0020,
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SCB_QUEUED_FOR_DONE = 0x0040,
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SCB_PAGED_OUT = 0x0080,
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SCB_WAITINGQ = 0x0100,
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SCB_ASSIGNEDQ = 0x0200,
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SCB_SENTORDEREDTAG = 0x0400,
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SCB_MSGOUT_SDTR = 0x0800,
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SCB_MSGOUT_WDTR = 0x1000,
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SCB_ABORT = 0x2000
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} scb_flag;
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/*
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* The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
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* consists of a "hardware SCB" mirroring the fields availible on the card
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* and additional information the kernel stores for each transaction.
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*/
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struct hardware_scb {
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/*0*/ u_int8_t control;
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/*1*/ u_int8_t tcl; /* 4/1/3 bits */
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/*2*/ u_int8_t status;
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/*3*/ u_int8_t SG_segment_count;
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/*4*/ physaddr SG_list_pointer;
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/*8*/ u_int8_t residual_SG_segment_count;
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/*9*/ u_int8_t residual_data_count[3];
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/*12*/ physaddr data;
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/*16*/ u_int32_t datalen; /* Really only three bits, but its
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* faster to treat it as a long on
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* a quad boundary.
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*/
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/*20*/ physaddr cmdpointer;
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/*24*/ u_int8_t cmdlen;
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/*25*/ u_int8_t tag; /* Index into our kernel SCB array.
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* Also used as the tag for tagged I/O
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*/
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#define SCB_PIO_TRANSFER_SIZE 26 /* amount we need to upload/download
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* via PIO to initialize a transaction.
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*/
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/*26*/ u_int8_t next; /* Used for threading SCBs in the
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* "Waiting for Selection" and
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* "Disconnected SCB" lists down
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* in the sequencer.
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*/
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/*27*/ u_int8_t prev;
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/*28*/ u_int32_t pad; /*
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* Unused by the kernel, but we require
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* the padding so that the array of
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* hardware SCBs is alligned on 32 byte
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* boundaries so the sequencer can
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* index them easily.
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*/
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};
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struct scb {
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struct hardware_scb *hscb;
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STAILQ_ENTRY(scb) links; /* for chaining */
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struct scsi_xfer *xs; /* the scsi_xfer for this cmd */
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scb_flag flags;
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struct ahc_dma_seg *ahc_dma;/* Pointer to SG segments */
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struct scsi_sense sense_cmd;
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u_int8_t position;/* Position in card's scbarray */
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};
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struct scb_data {
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struct hardware_scb *hscbs; /* Array of hardware SCBs */
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struct scb *scbarray[AHC_SCB_MAX]; /* Array of kernel SCBs */
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STAILQ_HEAD(, scb) free_scbs; /*
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* Pool of SCBs ready to be assigned
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* commands to execute.
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*/
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u_int8_t numscbs;
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u_int8_t maxhscbs; /* Number of SCBs on the card */
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u_int8_t maxscbs; /*
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* Max SCBs we allocate total including
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* any that will force us to page SCBs
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*/
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};
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struct ahc_busreset_args {
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struct ahc_softc *ahc;
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char bus;
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};
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struct ahc_softc {
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#if defined(__FreeBSD__)
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int unit;
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#elif defined(__NetBSD__)
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struct device sc_dev;
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void *sc_ih;
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bus_chipset_tag_t sc_bc;
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bus_io_handle_t sc_ioh;
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#endif
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ahc_type type;
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ahc_flag flags;
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#if defined(__FreeBSD__)
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u_int32_t baseport;
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#endif
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volatile u_int8_t *maddr;
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struct scb_data *scb_data;
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struct ahc_busreset_args busreset_args;
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struct ahc_busreset_args busreset_args_b;
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struct scsi_link sc_link;
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struct scsi_link sc_link_b; /* Second bus for Twin channel cards */
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STAILQ_HEAD(, scb) waiting_scbs;/*
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* SCBs waiting ready to go but
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* waiting for space in the QINFIFO.
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*/
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u_int8_t activescbs;
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u_int16_t needsdtr_orig; /* Targets we initiate sync neg with */
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u_int16_t needwdtr_orig; /* Targets we initiate wide neg with */
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u_int16_t needsdtr; /* Current list of negotiated targets */
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u_int16_t needwdtr; /* Current list of negotiated targets */
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u_int16_t sdtrpending; /* Pending SDTR to these targets */
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u_int16_t wdtrpending; /* Pending WDTR to these targets */
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u_int16_t tagenable; /* Targets that can handle tags */
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u_int16_t orderedtag; /* Targets to use ordered tag on */
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u_int16_t discenable; /* Targets allowed to disconnect */
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u_int8_t our_id; /* our scsi id */
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u_int8_t our_id_b; /* B channel scsi id */
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u_int8_t qcntmask; /*
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* Mask of valid registers in the
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* Q*CNT registers.
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*/
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u_int8_t qfullcount; /*
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* The maximum number of entries
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* storable in the Q*FIFOs.
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*/
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u_int8_t curqincnt; /*
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* The current value we "think" the
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* QINCNT has. The reason it is
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* "think" is that this is a cached
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* value that is only updated when
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* curqincount == qfullcount to reduce
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* the amount of accesses made to the
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* card.
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*/
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u_int8_t unpause;
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u_int8_t pause;
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u_int8_t in_timeout;
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u_int8_t in_reset;
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#define CHANNEL_A_RESET 0x01
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#define CHANNEL_B_RESET 0x02
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};
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struct full_ahc_softc {
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struct ahc_softc softc;
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struct scb_data scb_data_storage;
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};
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/* #define AHC_DEBUG */
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#ifdef AHC_DEBUG
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/* Different debugging levels used when AHC_DEBUG is defined */
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#define AHC_SHOWMISC 0x0001
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#define AHC_SHOWCMDS 0x0002
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#define AHC_SHOWSCBS 0x0004
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#define AHC_SHOWABORTS 0x0008
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#define AHC_SHOWSENSE 0x0010
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#define AHC_SHOWSCBCNT 0x0020
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extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */
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#endif
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#if defined(__FreeBSD__)
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char *ahc_name __P((struct ahc_softc *ahc));
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struct ahc_softc *ahc_alloc __P((int unit, u_int32_t io_base,
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vm_offset_t maddr, ahc_type type,
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ahc_flag flags, struct scb_data *scb_data));
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#elif defined(__NetBSD__)
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#define ahc_name(ahc) (ahc)->sc_dev.dv_xname
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void ahc_construct __P((struct ahc_softc *ahc, bus_chipset_tag_t bc, bus_io_handle_t ioh, ahc_type type, ahc_flag flags));
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#endif
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void ahc_reset __P((struct ahc_softc *ahc));
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void ahc_free __P((struct ahc_softc *));
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int ahc_init __P((struct ahc_softc *));
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int ahc_attach __P((struct ahc_softc *));
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#if defined(__FreeBSD__)
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void ahc_intr __P((void *arg));
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#elif defined(__NetBSD__)
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int ahc_intr __P((void *arg));
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#endif
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#if defined(__FreeBSD__)
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static __inline u_int8_t ahc_inb __P((struct ahc_softc *ahc, u_int32_t port));
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static __inline void ahc_outb __P((struct ahc_softc *ahc, u_int32_t port,
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u_int8_t val));
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static __inline void ahc_outsb __P((struct ahc_softc *ahc, u_int32_t port,
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u_int8_t *valp, size_t size));
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static __inline u_int8_t
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ahc_inb(ahc, port)
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struct ahc_softc *ahc;
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u_int32_t port;
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{
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if (ahc->maddr != NULL)
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return ahc->maddr[port];
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else
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return inb(ahc->baseport + port);
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}
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static __inline void
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ahc_outb(ahc, port, val)
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struct ahc_softc *ahc;
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u_int32_t port;
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u_int8_t val;
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{
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if (ahc->maddr != NULL)
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ahc->maddr[port] = val;
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else
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outb(ahc->baseport + port, val);
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}
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static __inline void
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ahc_outsb(ahc, port, valp, size)
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struct ahc_softc *ahc;
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u_int32_t port;
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u_int8_t *valp;
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size_t size;
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{
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if (ahc->maddr != NULL) {
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__asm __volatile("
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cld;
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1: lodsb;
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movb %%al,(%0);
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loop 1b" :
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:
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"r" ((ahc)->maddr + (port)),
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"S" ((valp)), "c" ((size)) :
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"%esi", "%ecx", "%eax");
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} else
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outsb(ahc->baseport + port, valp, size);
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}
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#elif defined(__NetBSD__)
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#define ahc_inb(ahc, port) \
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bus_io_read_1((ahc)->sc_bc, (ahc)->sc_ioh, port)
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#define ahc_outb(ahc, port, val) \
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bus_io_write_1((ahc)->sc_bc, (ahc)->sc_ioh, port, val)
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#define ahc_outsb(ahc, port, valp, size) \
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bus_io_write_multi_1((ahc)->sc_bc, (ahc)->sc_ioh, port, valp, size)
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#endif
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#endif /* _AIC7XXX_H_ */
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