318224bbe6
Make the amd64/pmap code aware of nested page table mappings used by bhyve
guests. This allows bhyve to associate each guest with its own vmspace and
deal with nested page faults in the context of that vmspace. This also
enables features like accessed/dirty bit tracking, swapping to disk and
transparent superpage promotions of guest memory.
Guest vmspace:
Each bhyve guest has a unique vmspace to represent the physical memory
allocated to the guest. Each memory segment allocated by the guest is
mapped into the guest's address space via the 'vmspace->vm_map' and is
backed by an object of type OBJT_DEFAULT.
pmap types:
The amd64/pmap now understands two types of pmaps: PT_X86 and PT_EPT.
The PT_X86 pmap type is used by the vmspace associated with the host kernel
as well as user processes executing on the host. The PT_EPT pmap is used by
the vmspace associated with a bhyve guest.
Page Table Entries:
The EPT page table entries as mostly similar in functionality to regular
page table entries although there are some differences in terms of what
bits are used to express that functionality. For e.g. the dirty bit is
represented by bit 9 in the nested PTE as opposed to bit 6 in the regular
x86 PTE. Therefore the bitmask representing the dirty bit is now computed
at runtime based on the type of the pmap. Thus PG_M that was previously a
macro now becomes a local variable that is initialized at runtime using
'pmap_modified_bit(pmap)'.
An additional wrinkle associated with EPT mappings is that older Intel
processors don't have hardware support for tracking accessed/dirty bits in
the PTE. This means that the amd64/pmap code needs to emulate these bits to
provide proper accounting to the VM subsystem. This is achieved by using
the following mapping for EPT entries that need emulation of A/D bits:
Bit Position Interpreted By
PG_V 52 software (accessed bit emulation handler)
PG_RW 53 software (dirty bit emulation handler)
PG_A 0 hardware (aka EPT_PG_RD)
PG_M 1 hardware (aka EPT_PG_WR)
The idea to use the mapping listed above for A/D bit emulation came from
Alan Cox (alc@).
The final difference with respect to x86 PTEs is that some EPT implementations
do not support superpage mappings. This is recorded in the 'pm_flags' field
of the pmap.
TLB invalidation:
The amd64/pmap code has a number of ways to do invalidation of mappings
that may be cached in the TLB: single page, multiple pages in a range or the
entire TLB. All of these funnel into a single EPT invalidation routine called
'pmap_invalidate_ept()'. This routine bumps up the EPT generation number and
sends an IPI to the host cpus that are executing the guest's vcpus. On a
subsequent entry into the guest it will detect that the EPT has changed and
invalidate the mappings from the TLB.
Guest memory access:
Since the guest memory is no longer wired we need to hold the host physical
page that backs the guest physical page before we can access it. The helper
functions 'vm_gpa_hold()/vm_gpa_release()' are available for this purpose.
PCI passthru:
Guest's with PCI passthru devices will wire the entire guest physical address
space. The MMIO BAR associated with the passthru device is backed by a
vm_object of type OBJT_SG. An IOMMU domain is created only for guest's that
have one or more PCI passthru devices attached to them.
Limitations:
There isn't a way to map a guest physical page without execute permissions.
This is because the amd64/pmap code interprets the guest physical mappings as
user mappings since they are numerically below VM_MAXUSER_ADDRESS. Since PG_U
shares the same bit position as EPT_PG_EXECUTE all guest mappings become
automatically executable.
Thanks to Alan Cox and Konstantin Belousov for their rigorous code reviews
as well as their support and encouragement.
Thanks for John Baldwin for reviewing the use of OBJT_SG as the backing
object for pci passthru mmio regions.
Special thanks to Peter Holm for testing the patch on short notice.
Approved by: re
Discussed with: grehan
Reviewed by: alc, kib
Tested by: pho
131 lines
4.3 KiB
C
131 lines
4.3 KiB
C
/*-
|
|
* Copyright (c) 2012 NetApp, Inc.
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
|
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
* SUCH DAMAGE.
|
|
*
|
|
* $FreeBSD$
|
|
*/
|
|
|
|
#ifndef _VMM_INSTRUCTION_EMUL_H_
|
|
#define _VMM_INSTRUCTION_EMUL_H_
|
|
|
|
/*
|
|
* The data structures 'vie' and 'vie_op' are meant to be opaque to the
|
|
* consumers of instruction decoding. The only reason why their contents
|
|
* need to be exposed is because they are part of the 'vm_exit' structure.
|
|
*/
|
|
struct vie_op {
|
|
uint8_t op_byte; /* actual opcode byte */
|
|
uint8_t op_type; /* type of operation (e.g. MOV) */
|
|
uint16_t op_flags;
|
|
};
|
|
|
|
#define VIE_INST_SIZE 15
|
|
struct vie {
|
|
uint8_t inst[VIE_INST_SIZE]; /* instruction bytes */
|
|
uint8_t num_valid; /* size of the instruction */
|
|
uint8_t num_processed;
|
|
|
|
uint8_t rex_w:1, /* REX prefix */
|
|
rex_r:1,
|
|
rex_x:1,
|
|
rex_b:1,
|
|
rex_present:1;
|
|
|
|
uint8_t mod:2, /* ModRM byte */
|
|
reg:4,
|
|
rm:4;
|
|
|
|
uint8_t ss:2, /* SIB byte */
|
|
index:4,
|
|
base:4;
|
|
|
|
uint8_t disp_bytes;
|
|
uint8_t imm_bytes;
|
|
|
|
uint8_t scale;
|
|
int base_register; /* VM_REG_GUEST_xyz */
|
|
int index_register; /* VM_REG_GUEST_xyz */
|
|
|
|
int64_t displacement; /* optional addr displacement */
|
|
int64_t immediate; /* optional immediate operand */
|
|
|
|
uint8_t decoded; /* set to 1 if successfully decoded */
|
|
|
|
struct vie_op op; /* opcode description */
|
|
};
|
|
|
|
/*
|
|
* Callback functions to read and write memory regions.
|
|
*/
|
|
typedef int (*mem_region_read_t)(void *vm, int cpuid, uint64_t gpa,
|
|
uint64_t *rval, int rsize, void *arg);
|
|
|
|
typedef int (*mem_region_write_t)(void *vm, int cpuid, uint64_t gpa,
|
|
uint64_t wval, int wsize, void *arg);
|
|
|
|
/*
|
|
* Emulate the decoded 'vie' instruction.
|
|
*
|
|
* The callbacks 'mrr' and 'mrw' emulate reads and writes to the memory region
|
|
* containing 'gpa'. 'mrarg' is an opaque argument that is passed into the
|
|
* callback functions.
|
|
*
|
|
* 'void *vm' should be 'struct vm *' when called from kernel context and
|
|
* 'struct vmctx *' when called from user context.
|
|
* s
|
|
*/
|
|
int vmm_emulate_instruction(void *vm, int cpuid, uint64_t gpa, struct vie *vie,
|
|
mem_region_read_t mrr, mem_region_write_t mrw,
|
|
void *mrarg);
|
|
|
|
#ifdef _KERNEL
|
|
/*
|
|
* APIs to fetch and decode the instruction from nested page fault handler.
|
|
*
|
|
* 'vie' must be initialized before calling 'vmm_fetch_instruction()'
|
|
*/
|
|
int vmm_fetch_instruction(struct vm *vm, int cpuid,
|
|
uint64_t rip, int inst_length, uint64_t cr3,
|
|
struct vie *vie);
|
|
|
|
void vie_init(struct vie *vie);
|
|
|
|
/*
|
|
* Decode the instruction fetched into 'vie' so it can be emulated.
|
|
*
|
|
* 'gla' is the guest linear address provided by the hardware assist
|
|
* that caused the nested page table fault. It is used to verify that
|
|
* the software instruction decoding is in agreement with the hardware.
|
|
*
|
|
* Some hardware assists do not provide the 'gla' to the hypervisor.
|
|
* To skip the 'gla' verification for this or any other reason pass
|
|
* in VIE_INVALID_GLA instead.
|
|
*/
|
|
#define VIE_INVALID_GLA (1UL << 63) /* a non-canonical address */
|
|
int vmm_decode_instruction(struct vm *vm, int cpuid,
|
|
uint64_t gla, struct vie *vie);
|
|
#endif /* _KERNEL */
|
|
|
|
#endif /* _VMM_INSTRUCTION_EMUL_H_ */
|